3 results about "Algorithm parallelization" patented technology

The invention discloses a method for parallelly and rapidly realizing fractal target detection, which comprises the following steps of: acquiring a sea radar signal matrix, carrying out stipulation summation and normalization processing, then carrying out peak value search, and determining fractal detection points; constructing a corresponding fractal matrix for each fractal detection point; constructing different detection sequences and detection values for each fractal matrix; setting different detection signal-to-noise ratios, and judging each fractal detection point by adopting a decision tree for multi-level condition judgment so as to determine the signal-to-noise ratio corresponding to the fractal detection point; and performing target detection based on the size of the signal-to-noise ratio. In order to solve the problem of long time consumption when a fractal target detection algorithm is carried out by using a CPU platform, the fractal target detection algorithm is parallelized, calculation is carried out by using a GPU, the realization of the fractal detection algorithm is accelerated, the calculation speed is improved, and radar signal processing is rapidly realized to meet the real-time requirement of radar data.

The invention discloses a merge tree enhancement method for a large-scale data set based on pointer doubling and parallelization. The method comprises the steps of obtaining a steepest rising path so as to determine a control area, proposing a horizontal enhancement method and a vertical enhancement method, determining a point set needing to be processed according to different enhancement methods, calculating a binary ancestor table of each key point (saddle point and extreme point), and parallelizing a binary ancestor table construction process so as to quickly find ancestor nodes of the key points. A key interval to which each rule point belongs is positioned by utilizing a multiplication algorithm, point sets corresponding to the key points are sequenced in parallel, the rule points are accurately integrated into a merge tree, and merge tree enhancement is quickly and effectively performed on a large-scale data set. According to the method, a merge tree enhancement process is optimized and innovated by combining a binary ancestor table, a pointer doubling algorithm and a parallelization technology, complex large-scale data can be processed, and horizontal enhancement and vertical enhancement of the merge tree are realized. The overall process is as shown in Figure 1.

This invention relates to the fields of information security and quantum-resistant computing, and discloses a hardware-accelerated parallel implementation method and system for quantum-resistant encryption algorithms. The method includes: configuring a parallelized quantum-resistant encryption core computing array; deploying a spiking neural network control module that simulates the random firing behavior of biological neurons, and connecting it to a power-compensating execution unit; monitoring key computing cycles and activating the module; using the non-periodic random pulses generated by the module to drive power consumption perturbation, deeply fusing instantaneous power consumption and noise; and dynamically adjusting neuron parameters through a feedback mechanism to make the total power consumption exhibit random characteristics similar to biological neural electrical signals. Through the above scheme, this invention disguises the encryption power consumption trajectory as random noise, resisting physical attacks such as differential power analysis without sacrificing computational performance, thereby improving the physical layer security and energy efficiency of the quantum-resistant encryption system.