5 results about "Algorithm parallelization" patented technology

The present invention discloses a parallelized finite element mesh stitching method for flow channels of reactor unit assemblies, belonging to the field of finite element mesh technology; the present invention classifies cavities according to their characteristics, and then stitches cavities of different categories using different methods. In addition to the original point stitching algorithm, the algorithm also adaptively applies a variety of algorithms such as particle swarm optimization, shortest path problem, and advancing wavefront method, and achieves high-efficiency stitching of large-scale meshes while ensuring the overall mesh quality through parallel processing of the algorithm and tetrahedron quality detection optimization algorithm. The present invention helps to optimize mesh quality, promote the application scenarios of large-scale parallel mesh division algorithms, fill the gap in three-dimensional mesh stitching technology, and further promote the application and development of mesh technology in the field of numerical calculation.

The invention discloses a method for parallelly and rapidly realizing fractal target detection, which comprises the following steps of: acquiring a sea radar signal matrix, carrying out stipulation summation and normalization processing, then carrying out peak value search, and determining fractal detection points; constructing a corresponding fractal matrix for each fractal detection point; constructing different detection sequences and detection values for each fractal matrix; setting different detection signal-to-noise ratios, and judging each fractal detection point by adopting a decision tree for multi-level condition judgment so as to determine the signal-to-noise ratio corresponding to the fractal detection point; and performing target detection based on the size of the signal-to-noise ratio. In order to solve the problem of long time consumption when a fractal target detection algorithm is carried out by using a CPU platform, the fractal target detection algorithm is parallelized, calculation is carried out by using a GPU, the realization of the fractal detection algorithm is accelerated, the calculation speed is improved, and radar signal processing is rapidly realized to meet the real-time requirement of radar data.

The invention discloses a merge tree enhancement method for a large-scale data set based on pointer doubling and parallelization. The method comprises the steps of obtaining a steepest rising path so as to determine a control area, proposing a horizontal enhancement method and a vertical enhancement method, determining a point set needing to be processed according to different enhancement methods, calculating a binary ancestor table of each key point (saddle point and extreme point), and parallelizing a binary ancestor table construction process so as to quickly find ancestor nodes of the key points. A key interval to which each rule point belongs is positioned by utilizing a multiplication algorithm, point sets corresponding to the key points are sequenced in parallel, the rule points are accurately integrated into a merge tree, and merge tree enhancement is quickly and effectively performed on a large-scale data set. According to the method, a merge tree enhancement process is optimized and innovated by combining a binary ancestor table, a pointer doubling algorithm and a parallelization technology, complex large-scale data can be processed, and horizontal enhancement and vertical enhancement of the merge tree are realized. The overall process is as shown in Figure 1.

This invention relates to the fields of information security and quantum-resistant computing, and discloses a hardware-accelerated parallel implementation method and system for quantum-resistant encryption algorithms. The method includes: configuring a parallelized quantum-resistant encryption core computing array; deploying a spiking neural network control module that simulates the random firing behavior of biological neurons, and connecting it to a power-compensating execution unit; monitoring key computing cycles and activating the module; using the non-periodic random pulses generated by the module to drive power consumption perturbation, deeply fusing instantaneous power consumption and noise; and dynamically adjusting neuron parameters through a feedback mechanism to make the total power consumption exhibit random characteristics similar to biological neural electrical signals. Through the above scheme, this invention disguises the encryption power consumption trajectory as random noise, resisting physical attacks such as differential power analysis without sacrificing computational performance, thereby improving the physical layer security and energy efficiency of the quantum-resistant encryption system.

The application belongs to the technical field of digital signal processing, and specifically discloses a space-time interference cancellation algorithm parallelization FPGA implementation device and method. The device comprises: an input vector generation module, which delays and arranges a reference signal of multiple channels to obtain a space-time input vector of the reference signal; a correlation matrix calculation module, which obtains an autocorrelation matrix and a cross-correlation vector; a matrix decomposition module, which performs matrix decomposition on the autocorrelation matrix to obtain an upper triangular matrix; a weight determination module, which solves the weight by using the upper triangular matrix and the cross-correlation vector to obtain an optimal weight; a delay matching module, which delays the reference signal, aligns the reference signal and the optimal weight in time sequence, and obtains a delay matching result; and a weighted combination module, which weights the reference signal after time sequence alignment according to the optimal weight, combines the weighted signal and a received signal, and realizes interference cancellation of the received signal. The application can improve real-time tracking capability and reduce processing delay.