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Structure for reducing wafer leakage currents and plasma processing chamber with structure

A plasma and leakage current technology, applied in circuits, discharge tubes, electrical components, etc., can solve problems such as increasing the probability of wafer device damage, shortening the service life of semiconductor devices, and wafer device damage, and improving quality and performance. , the effect of increasing the service life and reducing the probability of damage

Active Publication Date: 2014-05-21
ADVANCED MICRO FAB EQUIP INC CHINA
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The DC power supply of the commonly used plasma processing chamber at present, at the moment of starting plasma etching, that is, the moment when the DC power supply is powered on, will form a leakage current peak value (spike) passing through the entire series circuit, that is, passing through the wafer. , and usually cause wafer device damage (PID) due to the large peak value of the leakage current; at the same time, during the subsequent plasma etching process after power-on, the leakage current will gradually approach a steady-state value, and the steady-state value The state value will also be maintained at a large current value, and when the leakage current has a large steady state value, it will also increase the damage probability of the wafer device, resulting in a shortened service life of the semiconductor device after fabrication

Method used

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  • Structure for reducing wafer leakage currents and plasma processing chamber with structure
  • Structure for reducing wafer leakage currents and plasma processing chamber with structure
  • Structure for reducing wafer leakage currents and plasma processing chamber with structure

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Embodiment Construction

[0027] The following combination Figure 3 ~ Figure 6 , the present invention is described in detail through preferred specific embodiments.

[0028] Such as image 3 and Figure 4 As shown, the structure for reducing wafer leakage current provided by the present invention is arranged in a plasma processing chamber, the plasma processing chamber includes a base, and the ESC 2 arranged on the surface of the base is embedded in the ESC 2 The DC electrode in, and the DC power supply 1 connected to the ESC 2; the wafer 3 to be etched is installed on the ESC 2. The structure for reducing wafer leakage current is a current-limiting impedance R3 connected in series between the output terminal of the DC power supply 1 and the ESC 2 .

[0029] Before the plasma processing chamber is powered on, since the wafer 3 has not been adsorbed by the ESC 2, the impedance formed between the wafer 3 and the ESC 2 can be equivalent to a capacitor C1; and since the plasma 4 has not yet been forme...

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Abstract

The invention provides a structure for reducing wafer leakage currents. The structure is arranged in a plasma processing chamber which comprises a base, an electrostatic chuck (ESC) arranged on the surface of the base, a direct-current electrode buried in the ESC and a direct-current power supply connected with the ESC. A wafer to be etched is mounted on the ESC, the structure is current-limiting impedance connected between the output end of the direct-current power supply and the ESC, and the resistance is larger than 1Momega. The invention further provides the plasma processing chamber with the structure. By means of the structure and the plasma processing chamber, the leakage current peak value through the wafer during electrifying of the plasma processing chamber and the leakage current steady-state value through the wafer when electrifying is ended can be effectively reduced, the damage probability of the wafer during etching is reduced apparently, and accordingly, the quality and the performance of a made semiconductor device can be effectively enhanced, and the service life is prolonged.

Description

technical field [0001] The invention relates to the field of plasma processing devices, in particular to a structure capable of reducing the peak value of wafer leakage current and reducing the steady-state value of leakage current, and a plasma processing chamber provided with the structure. Background technique [0002] During the plasma etching process of the wafer, a base is set in the plasma processing chamber, a support on the surface of the base, the support is usually an electrostatic chuck (ESC), and a DC electrode embedded in the electrostatic chuck , and a DC power supply connected to the electrostatic chuck. A wafer to be etched is mounted on the electrostatic chuck. [0003] When etching, first turn on the DC power supply and apply energy to the etching reaction gas (composed of one or more gases) in the plasma processing chamber to excite the gas to form plasma, and in the plasma processing chamber there is Radio frequency (RF) energy, microwave energy, and / o...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01J37/32
Inventor 罗伟义梁洁丁冬平倪图强
Owner ADVANCED MICRO FAB EQUIP INC CHINA
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