Non-data-aided parallel clock synchronizing method and system

A technology without data assistance and clock synchronization, applied in the field of communication, can solve the problems of unsuitable multi-path channel environment and long convergence time of Gardner algorithm, so as to meet the processing requirements of high-speed and large data volume, shorten processing delay, The effect of stable performance

Inactive Publication Date: 2014-05-21
TSINGHUA UNIV
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

[0004] However, the traditional Gardner algorithm takes a long time to converge and is significantl...

Method used

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  • Non-data-aided parallel clock synchronizing method and system
  • Non-data-aided parallel clock synchronizing method and system
  • Non-data-aided parallel clock synchronizing method and system

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Embodiment 1

[0071] This embodiment is applicable to the wireless burst communication mode, that is, there is a gap between data transmissions, frame header synchronization needs to be completed again for each burst communication, and all states need to be initialized. Assuming that the input data rate is N times the symbol rate, if the symbol period is T, the sampling clock period is T S =T / N; the data length of the segment buffer and the calculation of the sampling clock deviation is M*N; the parallel input data is N P way, parallel output is N P / N way. Parallel input N p After the channel data is interpolated and controlled, the output is N P *K / N channel data. The interpolation algorithm adopts cubic interpolation, and each K-channel input forms a group to obtain one interpolation output. The final output of the parallel interpolator is N P / N way. In this example, N, M, N P , K are all positive integers, set N=4, N P =8, M=512, K=4.

[0072] The non-data-assisted parallel c...

Embodiment 2

[0097] This embodiment considers a continuous communication mode, that is, data is sent all the time without any initializeable time slot. In this case, if the input data is always in the under-sampling state, when the data is buffered, it needs to be continuously moved backwards from the buffer to ensure the continuity of the data. No matter how big the buffer space is, there will always be a situation where the backward move exceeds the buffer space. In this case, the embodiments for the burst communication mode are no longer applicable.

[0098] In this embodiment, it is still assumed that the rate of the input data is N times the symbol symbol rate, if the symbol period of the symbol is T, the sampling clock period is T S =T / N; the data length of the segment buffer and the calculation of the sampling clock deviation is M*N; the parallel input data is N P way, parallel output is N P / N way. where the input of the interpolation control is N P way, the output is N P *K / ...

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Abstract

The invention discloses a non-data-aided parallel clock synchronizing method and system. The method comprises S1, caching received data; S2, performing parallel clock error detection on the cache data to obtain a sampling clock skew; S3, according to the sampling clock skew, performing parallel interpolation control on the cache data; S4, performing interpolation on the paralleled data to complete sampling clock error compensation; S5, outputting the interpolated paralleled data to achieve clock synchronization.

Description

technical field [0001] The invention relates to the technical field of communication, in particular to a data-assisted parallel clock synchronization method and system. Background technique [0002] In digital communications, a message is composed of a sequence of information symbols, usually of the same duration. The duration of the symbol sequence is usually controlled by a fixed frequency sampling clock. In order to ensure that the receiving end is consistent with the symbol sequence of the transmitting end, the duration (frequency) of the sampling clock at both ends of the transceiver needs to be fully synchronized with the starting position (phase). [0003] The existing data-free clock synchronization method is the data-free clock recovery algorithm proposed by Gardner and applied to binary phase shift keying BPSK and quaternary phase shift keying QPSK. This method has been widely used in the Gaussian channel environment . [0004] However, the traditional Gardner a...

Claims

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Application Information

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IPC IPC(8): H04J3/06
Inventor 张彧曾安辉吴义辰姜龙吴钊
Owner TSINGHUA UNIV
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