Through si via radio frequency test structure and parasitic extracting method thereof

Abstract

The invention discloses a through si via radio frequency test structure which is formed by a first test structure and a second open circuit de-embedding structure. The first test structure comprises a first port and a second port of a GSG bonding pad structure; signal ends of the first port and the second port are connected in a short circuit manner by a first top metal; a tested through si via is arranged between signal ends of the first port and the second port; the top of the tested through si via is connected with the first top metal; the bottom of tested through si via is connected with a second back metal; and grounding terminals of the first port and the second port are respectively connected with the second back metal through a grounding through si via array. The second open circuit de-embedding structure and the first test structure, after the first top metal and tested through si via are removed, are the same in structure. The invention also discloses a parasitic extracting method of the through si via radio frequency test structure. According to the invention, the accuracy of testing the parasitic resistance and inductance of the through si via can be improved, and the test structure area and the process cost can be reduced.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a radio frequency testing structure of through-silicon holes. The invention also relates to a parasitic extraction method of the radio frequency test structure of the through-silicon hole. Background technique [0002] The Through Silicon Via (TSV) process is an emerging integrated circuit manufacturing process. The circuit fabricated on the upper surface of the silicon wafer is connected to the back of the silicon wafer through the metal filled in the silicon via. Combined with the three-dimensional packaging process, it makes IC layout has evolved from traditional two-dimensional side-by-side arrangement to more advanced three-dimensional stacking, so that component packaging is more compact, and by shortening the distance between chip leads, the frequency characteristics and power characteristics of the circuit can be greatly improved. The through...

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Problems solved by technology

[0006] The above-mentioned existing structure can extract relatively accurate parasitic inductance and parasitic resistance, but there are also some defects, which lead to certain errors in test results. Two TSVs connected in series will produce mutual inductance, which is difficult to remove, although it can be removed by adding The method of increasing the distance between two TSVs can reduce or eliminate the influence of mutual inductance, but this will also increase the parasitic resistance of the connection part on the back of the two TSVs, and will also increase the area; in addition, from the perspective of de-embedding, this method needs to be equipped with An open circuit structure and a via structure, there are many de-embedding structures, occupying a large area of ​​the chip, and the cost is high

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