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Method and system for channel allocation, release, and data transmission based on pcie bus

A channel allocation and channel release technology, applied in electrical digital data processing, instruments, etc., can solve the problems of high processor occupancy rate at the sending end and receiving end, lack of effective management of resource pools, and low PCIe bus utilization

Active Publication Date: 2016-08-17
SUZHOU KEDA TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] For this reason, the technical problem to be solved by the present invention is that the existing technology lacks effective management methods for resource pools, resulting in low utilization of the PCIe bus during data transfer, and high processor occupancy at the sending end and receiving end, thus proposing a A PCIe bus-based channel allocation, release, and data transmission method and system capable of effectively managing resource pools

Method used

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  • Method and system for channel allocation, release, and data transmission based on pcie bus
  • Method and system for channel allocation, release, and data transmission based on pcie bus
  • Method and system for channel allocation, release, and data transmission based on pcie bus

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Embodiment 1

[0101] This embodiment provides a method for channel allocation based on the PCIe bus, such as figure 1 shown, including the following steps:

[0102] S1: Divide a management area and a resource pool in the PCIe space, and the resource pool includes several free areas that can be used to establish channels.

[0103] S2: Store a free area linked list corresponding to the free area in the management area, and record the position and space size of each free area in the free area linked list.

[0104] S3: Receive the channel allocation application, and find the free area corresponding to the channel allocation application in the free area list.

[0105] S4: Divide the channel connecting the sending end and the receiving end in the corresponding idle area.

[0106] In a common PCIe bus-based architecture, RC (root complex) serves as a master control to connect to one EP (end point), or connect multiple EPs through a PCIe bridge chip. RC accesses the address space of the EP memor...

Embodiment 2

[0128] This embodiment provides a method for channel release based on the PCIe bus, such as figure 2 shown, including the following steps:

[0129] A1: A management area and a resource pool are divided in the PCIe space, and the resource pool includes several channels connecting the sending end and the receiving end.

[0130] A2: Determine whether there is a channel that stops writing data, if so, go to step A3, otherwise repeat this step.

[0131] A3: Determine whether there is a request to forcibly release the channel, if not, proceed to step A4, and if yes, proceed to step A5.

[0132] A4: Determine whether there is data in the channel, if not, go to step A5, if yes, repeat this step.

[0133] A5: Release the channel.

[0134] In the PCIe bus-based channel release method described in this embodiment, when the sending end no longer sends new data, the channel stops reading data, but the data in the channel will continue to be transmitted to the receiving end. The release ...

Embodiment 3

[0144] On the basis of Embodiment 1 and Embodiment 2, the design of the channel state machine is a critical step in the process of channel allocation and release, and it is an indispensable part. The channel creation is initiated at the sending end until the receiving end Sensing this newly created channel and notifying the sender is inseparable from the state machine, including the release of the channel in mandatory and non-mandatory mode, which requires the state machine to coordinate the sending and receiving parties. The notification method can be MSI or through Thread polling. The state machine diagram in the process of channel allocation is as follows: Figure 11 As shown, the state machine diagram in the channel release process is as follows Figure 12 shown.

[0145] This embodiment also provides a design scheme of a channel state machine in a specific application, as follows:

[0146] Channel status includes the following:

[0147] CHANNEL_FREE,

[0148] CHANNEL...

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Abstract

The invention provides PCIe (Peripheral Component Interface express) bus based channel allocating, releasing, data transmitting method and system. The PCIe bus based channel allocating method comprises the following steps: dividing a management area from PCIe space, finding an idle area adapted to channel allocating application through an idle area chain table stored in the management area and marking off a channel for connecting a sending end with a receiving end, wherein the PCIe space represents a window of RC (Root Complex) accessing an EP (End Point) storage area, the RC is capable of obtaining the channel allocating application first time and identifying the channel allocating application in the management area; both the management area and a resource pool are located in the PCIe space to ensure that the management area is capable of finding the idle area adapted to the channel allocating application through the idle area chain table stored in the management area first time and marking off the channel for connecting a sending end with a receiving end from the resource pool. Therefore, the PCIe bus based channel allocating, releasing, data transmitting method and system, provided by the invention, are capable of effectively managing the resource pool.

Description

technical field [0001] The invention relates to a method and system for channel allocation, release and data transmission. Specifically, it relates to a PCIe bus-based channel allocation, release, and data transmission method and system. Background technique [0002] As a local bus, PCIe currently includes a PCIe controller in most processors to connect external devices for data transmission between peripheral devices and the processor. Many concepts in the Internet now appear in the PCIe bus, such as switching, routing, etc. The PCIe bus is also composed of several layers, mainly divided into transaction layer, data link layer and physical layer, which are quite similar to the network protocol stack. similar. As an "end-to-end data transmission method", a PCIe link includes sending logic and receiving logic, which can be composed of multiple Lanes, that is, X1, X2, X8, X16, etc. in the usual sense. After the PCIe bus specification has experienced V1.0, V1.0a, V1.1, V2.0 ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/20
Inventor 周新星王黔川曹李军陈卫东
Owner SUZHOU KEDA TECH
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