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Method for forming guide circuit of semiconductor chip package

A chip packaging and wiring technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as increased manufacturing costs, reduced product qualification rates, and complex manufacturing processes, and achieves high precision and promotes effective utilization. Effect

Active Publication Date: 2014-06-11
XIAMEN MSSB TECHNOLOGY CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The semiconductor chip packaging structure developed and used in the early stage is a TAB (Tape automated bonding) technology, but in the packaging structure of the TAB technology, there are multiple pads on the pad-mounting surface of the semiconductor chip (pad-mounting surface). The outer lead portions (outer lead portions) extending outward from the bonding die pad will result in a larger package size, which is not conducive to realizing the high density (high density) requirements of the semiconductor chip packaging structure; and the recent development and use of semiconductor chips The packaging structure belongs to a chip scale package type (chip size package type), and has derived a variety of different processes and structures, and the process and structure of this chip scale package type (chip size package type) can be solved TAB technology will cause the problem of larger package size, but there are still problems such as complicated process, lower product qualification rate, and relatively higher manufacturing cost among the various known processes and / or structures, which need to be further improved

Method used

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  • Method for forming guide circuit of semiconductor chip package
  • Method for forming guide circuit of semiconductor chip package
  • Method for forming guide circuit of semiconductor chip package

Examples

Experimental program
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Effect test

no. 1 example ＞

[0053] Please refer to FIG. 1(A)-FIG. 1(L), which are schematic flow charts of an embodiment of a method for forming a semiconductor chip package and its conductive lines (with a single-layer conductive line) according to the present invention. The semiconductor chip package 1 of the present invention, as shown in FIG. a bonding pad (bonding pad) 11; at least one dielectric layer (dielectric layer) 20, which is covered on the bonding pad surface 12 of the chip 10; and at least one conductive line 30 is disposed in the dielectric layer 20 One end of each conductive line 30 is electrically connected to a pad 11 on the chip 10, and the other end extends outward and is exposed outside the dielectric layer 20 to form a solder point 31. For electrical connection with a pre-arranged solder point on a substrate (not shown), so that the semiconductor chip 10 is mounted and combined on the substrate; generally speaking, when the surface 12 of the solder pad of the semiconductor chip 10 ...

no. 2 example ＞

[0069] Referring to FIG. 2(A)-2(N), they are schematic flowcharts of another embodiment (with double-layer conductive lines) of the method for forming the semiconductor chip package and its conductive lines according to the present invention. The semiconductor chip package structure 2 of this embodiment is shown in Figure 2 (N), comprising: a semiconductor chip 10, which has a pad surface 12, and a plurality of pads 11 are arranged on the pad surface 12; at least one Dielectric layer 20, which is covered on the bonding pad surface 12 of the chip 10; The pad 11 is electrically connected, and the other end extends outward and is exposed outside the dielectric layer 20 to form a solder point 31 for a solder point pre-disposed on a substrate (not shown). point electrical connection, so that the semiconductor chip 10 is installed and combined on the substrate; the semiconductor chip package structure 2 of the present embodiment is substantially the same as the semiconductor chip pa...

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PUM

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Abstract

The invention provides a method for forming a guide circuit of semiconductor chip package. The method comprises the steps that a first dielectric layer coats the surface of each welding pad of the chip, and a corresponding groove is formed in each welding pad in exposure and development modes; then second dielectric layers are coated, and circuit grooves are formed corresponding to all the welding pads and the grooves in exposure and development modes; all the circuit grooves are filled with conductive metal medium, for example, silver paste is used for printing to respectively form a guide circuit; third dielectric layers are then coated, a corresponding groove is formed in one end of each guide circuit in exposure and development modes, and the corresponding grooves are filled with conductive metal medium so that a welding spot can be formed and be exposed to the outside of an outer dielectric layer. Accordingly, the precision of the packaging structure of the semiconductor chip can be improved, the wiring space on the chip can be better effectively utilized, the using efficiency of wafers is improved, and the percent of pass of the packaging process is greatly improved.

Description

technical field [0001] The present invention relates to a method for forming a conducting line of a semiconductor chip package, in particular to a method for forming an outwardly extending conducting line and a welding spot for a plurality of welding pads on a semiconductor chip, so that the semiconductor chip can rely on each Conducting lines and soldering points are electrically connected and installed on a substrate. Background technique [0002] With the development of semiconductor manufacturing process, semiconductor chip packaging structure (or called semiconductor chip device) has a variety of different manufacturing processes and structures, such as China Taiwan Invention Patent Publication No. 434848 "Semiconductor Chip Device and Its Packaging Method" and its four Additional patent cases include: Announcement No. 466715 (Addition 1), Announcement No. 495933 (Addition 2), Announcement No. 466716 (Addition 3), Announcement No. 503534 (Addition 4), and US Patent No. ...

Claims

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Application Information

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IPC IPC(8): H01L21/60
CPCH01L24/11H01L2224/11H01L2924/00012
Inventor 璩泽明马嵩荃
Owner XIAMEN MSSB TECHNOLOGY CO LTD