Double-loop control circuit of phase-shifted full-bridge synchronous rectification circuit
A synchronous rectification, phase-shifting full-bridge technology, applied in control/regulation systems, high-efficiency power electronic conversion, electrical components, etc., can solve the problems of different magnetic induction intensity, transformer loss of energy transfer function, etc.
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Embodiment 1
[0055] The dual-loop control circuit of the phase-shifted full-bridge synchronous rectification circuit, such as Figure 4 As shown, it includes a current sampling module and a microprocessor;
[0056] The current sampling module is used to detect the bus current of the phase-shifted full-bridge synchronous rectification circuit, and conduct the bus current of the phase-shifted full-bridge synchronous rectification circuit in the first phase according to the frequency of the PWM signal output by the microprocessor. Sampling to obtain the first current sampling value I1, sampling in the second phase according to the frequency of the PWM signal output by the microprocessor to obtain the second current sampling value I2, the difference between the first phase and the second phase is 180 degrees, and output the first The current sampling value I1 and the second current sampling value I2 are sent to the microprocessor;
[0057] The microprocessor, such as Figure 5 As shown, it i...
Embodiment 2
[0070] Based on the dual-loop control circuit of the phase-shifted full-bridge synchronous rectification circuit of Embodiment 1, the magnetic bias state control module calculates the forward bias correction value ΔAD, negative direction The process of offset correction value ΔBC is:
[0071] 1. ΔAD 0 =0, ΔBC 0 =0, ΔAD 0 is the initial value of forward bias correction value, ΔBC 0 is the initial value of the negative bias correction value; the initial value of n is 1;
[0072] 2. If I1 n ≥I2 n , and (I1 n -I2 n ) / F>a, proceed to step 3; if I1 n n , and (I2 n -I1 n ) / F>a, proceed to step 8; I1 n is the first current sampling value of the nth sampling period, I2 n is the second current sampling value of the nth sampling period, a is a positive number, preferably a is a positive number less than 10% (for example, a=5%), and F is the reference current (for example, F=1A);
[0073] 3. If ΔAD n-1 ≥0 and ΔBC n-1 =0, proceed to step 4; if ΔAD n-1 =0 and ΔBC n-1 >0, pr...
Embodiment 3
[0086] Based on the dual-loop control circuit of the phase-shifted full-bridge synchronous rectification circuit of embodiment two, the microprocessor, such as Figure 7 As shown, also includes a second comparison output module;
[0087] In the second comparison output module, an input terminal is connected to set the minimum phase shift value, and an input terminal is connected to the full-scale phase-shift value output by the first comparison output module, and the output limit phase-shift value; if the full-scale phase shift value is greater than If the minimum phase shift value is set, the output limit phase shift value is equal to the full scale phase shift value; if the full scale phase shift value is less than or equal to the set minimum phase shift value, the output limit phase shift value is equal to the set minimum phase shift value ; The set minimum phase shift value is greater than the maximum offset correction value Br;
[0088] In the third subtractor, the two i...
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