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Alignment pattern and wafer

A technology for aligning graphics and wafers, applied to electrical components, electrical solid devices, circuits, etc., can solve problems such as inability to complete measurement and difficult positioning, achieve high contrast and improve measurement efficiency

Active Publication Date: 2014-06-18
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the unique pattern of the existing technology is difficult to locate and cannot be measured

Method used

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  • Alignment pattern and wafer
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  • Alignment pattern and wafer

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Embodiment Construction

[0026] The alignment pattern and the wafer of the present invention will be described in more detail below in conjunction with schematic diagrams, wherein a preferred embodiment of the present invention is represented, and it should be understood that those skilled in the art can modify the present invention described here and still realize the present invention beneficial effect. Therefore, the following description should be understood as the broad knowledge of those skilled in the art, but not as a limitation of the present invention.

[0027] In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions and constructions are not described in detail since they would obscure the invention with unnecessary detail. It should be appreciated that in the development of any actual embodiment, numerous implementation details must be worked out to achieve the developer's specific goals, such as changing fr...

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Abstract

The invention discloses an alignment pattern which is used for aligning a wafer on a measurement machine table. The wafer comprises projection exposure areas in multiple arrays, every two adjacent projection exposure areas are isolated from each other through a cutting way, and the alignment pattern is located in the cutting ways on the lateral sides of the projection exposure areas. The invention further provides the wafer comprising the alignment pattern. In the alignment pattern, other interference patterns do not exist in the cutting ways on the lateral sides of the projection exposure areas, the ratio of contrast between the cutting ways and the alignment pattern is high, under an optical microscope of the measurement machine table, the alignment pattern and the background are sharply contrasted between black and white, and thus the position of the wafer can be accurately positioned, and the measurement efficiency can be improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor wafer alignment, in particular to an alignment pattern and a wafer. Background technique [0002] Semiconductor chip manufacturing includes multiple processes. After each process is implemented, it is necessary to use measurement and other means to monitor whether the process is up to standard. For example, for dielectric chemical vapor deposition (DCVD), dry etching (ETCH), wet etching (WET), chemical mechanical polishing (CMP) and other processes, after the process steps are completed, it is necessary to measure the specified position on the wafer The thickness or total thickness of the single-layer film; another example, photolithography (PHOTO), dry etching (ETCH) and other processes, after the process steps are completed, it is necessary to measure the characteristic dimension (CD) of the specified position on the wafer, etc. [0003] Taking the measurement of film thickness by a film...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/544
Inventor 吴佳宏
Owner SHANGHAI HUALI MICROELECTRONICS CORP