Assembly line successive approximation type analog-digital converter self-calibration method and device

Abstract

The invention discloses an assembly line successive approximation type analog-digital converter self-calibration method and device. The assembly line successive approximation type analog-digital converter self-calibration device comprises a first-stage successive approximation type analog-digital converter, a second-stage successive approximation type analog-digital converter, an operational amplifier and a digital calibration control logical circuit, wherein the first-stage successive approximation type analog-digital converter is used for completing data collection and analog-digital conversion on input signals, a pseudo random quantity with a known digital quantity is exerted on the first-stage successive approximation type analog-digital converter, the operational amplifier is used for amplifying remnant signals output by the first-stage successive approximation type analog-digital converter and transmitting the remnant signals to the second-stage successive approximation type analog-digital converter to conduct analog-digital conversion, and the digital calibration control logical circuit is used for conducting circulation calibration according to output and the pseudo random quantity of the first-stage successive approximation type analog-digital converter and the second-stage successive approximation type analog-digital converter to control gains of the operational amplifier, and obtaining data output. By means of the mode, the gains of the operational amplifier can be adjusted in real time, influences of factors such as the temperature and the supply voltage on the gains can be calibrated, and the effective accuracy of an ADC is accordingly improved.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a self-calibration method and device for sequentially comparing analog-to-digital converters in pipelines. Background technique [0002] As the microelectronics process enters the nanoscale process, the high-speed pipeline analog-to-digital converter (Pipeline Analog to Digital Convertor, Pipeline ADC) is becoming more and more difficult to realize in the advanced nanoscale process, and because of its huge power consumption, area, is becoming increasingly unacceptable. In this context, a new technology combining the Pipeline ADC with the Successive Approximation Register (SAR) ADC is proposed accordingly, which replaces the FLASH ADC in the single stage of the Pipeline ADC with the SAR ADC to Reduce power consumption and reduce area. Similar to the Pipeline ADC, since there is also an operational amplifier in the pipeline successive comparison analog-to-digital conv...

AI Technical Summary

Problems solved by technology

Therefore, under the condition that the gain and bandwidth of the operational amplifier meet the requirements, the matching degree of the operational amplifier and the capacitor determines the gain of the operational amplifier, but it puts forward higher requirements for the speed of the operational amplifier, that is, if the closed-loop amplification factor is 8, then The bandwidth of the operational amplifier needs to be 8 times of the closed-loop working bandwidth, so it has higher requirements on the working bandwidth of the operational amplifier, and it is difficult to realize that the operational amplifier needs to work at a higher bandwidth.

The open-loop-based Pipeline SAR ADC can achieve higher speed more easily, but the gain of the operational amplifier will shift with the process angle and temperature, which needs to be calibrated

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