P-BiCS structure and formation method thereof

Abstract

The invention discloses a P-BiCS structure and a formation method of the P-BiCS structure. The formation method includes the steps that a substrate and a pad layer are provided; a tubular channel pattern is formed on the top of the pad layer in a photoetching mode, and a groove is etched in the top of the pad layer; a first material is deposited in the groove so that a tubular channel sacrificial layer can be formed; second materials and third materials are deposited on the pad layer alternately so that a laminated structure of an insulation layer and a control grid sacrificial layer can be formed; vertical etched holes are formed in the laminated structure; the bottom of each vertical etched hole makes contact with the end of the tubular channel sacrificial layer; the tubular channel sacrificial layer is removed so that the vertical etched holes in the two ends of the tubular channel sacrificial layer can be communicated; the vertical etched holes are filled with polycrystalline silicon so that a U-shaped electric conduction channel can be formed; a center groove is etched in the laminated structure so that the portions, surrounding the two vertical sections of the U-shaped electric conduction channel, of the laminated structure can be spaced; the control grid sacrificial layer is removed; an electric charge capture composite layer is deposited and formed; a control grid electrode is deposited and formed. The P-BiCS structure with the metal grid electrode and the electric charge capture composite layer can be obtained, and the electrical property is good.

Description

technical field [0001] The invention belongs to the technical field of memory manufacturing, and in particular relates to a P-BiCS structure and a forming method thereof. Background technique [0002] Due to the scaling bottleneck of 2D NAND flash memory, 3D NAND has become the development direction in the field of memory technology. The researchers proposed a U-shaped vertical channel 3D and non-flash memory (pipe-shaped bit cost scalable, P-BiCS) structure combined with through-silicon via technology. The technology adopted in this P-BiCS is to stack multiple memory cells by embedding polysilicon channels in through-holes from the top layer to the bottom layer after alternately stacking gate electrode films and interlayer insulating films. That is, in P-BiCS, cells are connected on a U-shaped NAND string. [0003] The existing P-BiCS structure preparation method is: depositing SiO on the silicon substrate 2 Insulation layer; photoetching out the tubular channel pattern ...

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Problems solved by technology

[0005] The present invention aims to at least solve the technical problems existing in the prior art that metal gates cannot be used and high-k materials cannot be used as charge-trapping recombination layers

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