Slot gate and slot source SOILDMOS device
A trench gate and device technology, applied in the field of trench gate trench source SOI LDMOS devices, can solve problems such as low breakdown voltage, and achieve the effects of improving device withstand voltage, reducing device on-resistance, and short conduction paths
Inactive Publication Date: 2014-07-09
TIANJIN UNIVERSITY OF TECHNOLOGY
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However, the breakdown voltage of the slot-gate slot-drain structure is relatively low
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[0020] A trench-gate trench source SOI LDMOS device, such as figure 1 As shown, including substrate layer 1, buried oxide layer 2, active semiconductor layer 3, n + The drain region 6, the groove gate 7, the gate oxide layer 8, the dielectric buried layer 9, the groove source 10, the source electrode 11, the gate electrode 12, the p well 13 and the drain electrode 14 form an SOI LDMOS device, and the p well 13 is provided with n + source region 4 and p + The p-well ohmic contact region 5, the groove gate 7 and the groove source 10 are isolated by a dielectric buried layer 9; n + The upper part of the source region 4 is in contact with the gate oxide layer 8, the dielectric buried layer 9 and the groove source 10, p + The upper part of the p-well ohmic contact region 5 is in contact with the tank source 10 ; the bottom of the p-well 13 is in contact with the buried oxide layer 2 .
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The invention discloses a slot gate and slot source SOILDMOS device which is composed of a substrate layer, an oxygen buried layer, an active semiconductor layer, an n+ drain region, a slot gate, a gate oxygen layer, a medium buried layer, a slot source, a source electrode, a gate electrode, a p trap and a drain electrode. The n+ drain region and a p+p trap Ohmic contact area are arranged in the p trap, and the slot gate is isolated from the slot source through the medium buried layer. The upper portion of the n+ source area is connected with the gate oxygen layer, the medium buried layer and the slot source, and the upper portion of the p+p trap Ohmic contact area is connected with the slot source. The bottom of the p trap is connected with the oxygen buried layer. The slot gate and slot source SOILDMOS device has the advantages that in the slot gate and slot source SOILDMOS device, a high electric field is gathered in the longitudinal slot gate, transverse pressure resistance of the device is improved, a longitudinal electric field of the active semiconductor layer is evenly distributed under the action of the slot gate, and longitudinal pressure resistance of the device is improved. Due to the fact that the structures of the slot gate and the slot source are adopted, a longitudinal electric conduction channel is formed by the p trap and the longitudinal slot gate, and the conduction resistance of the device is obviously reduced.
Description
technical field [0001] The invention belongs to the technical field of semiconductor power devices, in particular to a groove-gate groove-source SOI LDMOS device. Background technique [0002] SOI (Silicon On Insulator) devices have the advantages of higher switching speed, ideal dielectric isolation, and low leakage current, and have attracted much attention in the design of intelligent integrated circuits. High breakdown voltage and low specific on-resistance have always been the hot research directions of SOI power devices, and various new device structures have been proposed continuously. With the continuous improvement of integrated circuit integration, the device size is getting smaller and smaller. How to increase the breakdown voltage of the device and reduce the specific on-resistance at the same time under the small device size has become a difficult point in the research of SOI power devices. [0003] In traditional SOI LDMOS devices, for small-sized devices, t...
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IPC IPC(8): H01L29/78H01L29/423H01L29/08
CPCH01L29/7824H01L29/0611H01L29/0886H01L29/4236H01L29/7825
Inventor 石艳梅刘继芝代红丽
Owner TIANJIN UNIVERSITY OF TECHNOLOGY