Array substrate and manufacturing method thereof
A technology of an array substrate and a manufacturing method, which is applied in the field of liquid crystal display devices, can solve problems such as increasing the size of liquid crystal display devices, and achieve the effects of increasing complexity and eliminating electrostatic damage
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specific Embodiment 1
[0032] This embodiment provides an array substrate. figure 1 It is a top view of the array substrate structure of this embodiment. figure 2 It is a cross-sectional view along A-A' of the array substrate structure of the present invention. figure 1 It exemplarily shows a pixel area limited by intersecting gate lines 1 and data lines 21, in which there are pixel electrodes 9 and common electrode lines 8, wherein the data lines 21 are used to provide the corresponding pixel electrodes 9 transmits data signals; the gate lines 1 are used to transmit scan signals to the corresponding pixel electrodes 9; there are a plurality of such pixel regions (not shown) on the array substrate. There are connecting lines between the common electrode lines 8 and the data lines 21 , and the connecting lines include a first connecting line 6 and a second connecting line 7 . Wherein, the first connection line 6 is specifically a strip structure arranged between the gate line 1 and the common elec...
specific Embodiment 2
[0036] This embodiment provides a method for manufacturing the array substrate in the first embodiment. Figure 3-10 The cross-sectional views of the array substrate structures manufactured by each process. like image 3 As shown, firstly, a first metal layer 12 is deposited on the substrate 10 by means of reactive sputtering, chemical vapor deposition, etc., and the material of the first metal layer 12 is aluminum, titanium, molybdenum and the like. The first metal layer 12 is patterned, and the patterning process includes coating photoresist, exposure, development, wet etching or dry etching the first metal layer, stripping photoresist and other conventional processes. The first metal layer 12 is patterned to obtain the gate and common electrode line 8 of the thin film transistor, such as Figure 4 shown.
[0037] Next, the gate insulating film 2 completely covering the gate and the common electrode line 8 is formed on the substrate 10, such as Figure 5 As shown, the ma...
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