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FPGA configuration method, FPGA configuration system and processor

A configuration method and processor technology, applied in the field of communication, can solve the problems of slow synchronization clock rate, low configuration data rate, and restricting the rapid startup of the system.

Inactive Publication Date: 2014-07-16
COMBA TELECOM SYST CHINA LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] The embodiment of the present invention provides a kind of FPGA configuration method and system, processor, in order to solve prior art when configuring FPGA, the synchronous clock speed of processor simulation will be relatively slow, the rate of transmission configuration data is low, thereby makes configuration FPGA The time-consuming will be relatively long, which restricts the problem of quick startup of the system

Method used

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  • FPGA configuration method, FPGA configuration system and processor
  • FPGA configuration method, FPGA configuration system and processor
  • FPGA configuration method, FPGA configuration system and processor

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Embodiment 1

[0024] by the above figure 2 It can be seen that in the prior art configuration timing of FPGA configuration, the timing of the synchronous clock signal and data is very close to the SPI bus timing generally used in serial communication, the only difference is that when the FPGA is configured, a series of bit streams are transmitted, and the transmitted The amount of data is relatively large, and the synchronous clock of the SPI bus is directly obtained by frequency division of the main frequency. Therefore, in order to solve the problem that the synchronous clock rate simulated by the processor is relatively slow and the rate of transmitting configuration data is low in the prior art, this Embodiment 1 of the invention proposes that SPI bus pins can be used to transmit synchronous clock signals and configuration data, thereby effectively increasing the transmission rate of configuration data and reducing the time-consuming configuration of FPGA.

[0025] In Embodiment 1 of t...

Embodiment 2

[0058] If the operating system running on the processor does not manage the SPI bus, such as the ucosⅡ system, the software directly controls the SPI bus pins to send data. At this time, the process of configuring the FPGA is as follows: Figure 6 As shown, the specific processing flow is as follows:

[0059] Step 61, if it is confirmed that the FPGA is configured in slave-serial mode, the processor will pull down the level of the PROGRAM_B pin from high level to low level, and after keeping the low level for a preset period of time (for example, 10μs), Pull up from low level to high level to notify FPGA to perform configuration initialization;

[0060] Step 62, if the processor detects that the level of the INIT_B pin is pulled up from a low level to a high level, it confirms that the FPGA has completed configuration initialization and is ready to receive configuration data;

[0061] Step 63, the processor confirms the storage address of the FPGA configuration data in the no...

Embodiment 3

[0082] If the operating system running on the processor can manage the SPI bus, that is, it has the SPI bus management function (such as an embedded Linux system), then the relevant interface of the operating system will send the data. Among them, the upper layer user of the operating system The space transmits the data to the interface, and then sends the data interface in the lower kernel space. At this time, the process of configuring the FPGA is as follows: Figure 8 As shown, the specific processing flow is as follows:

[0083] Step 81, calling the call interface of the operating system in the user space to reset each pin of the FPGA;

[0084] Step 82, reset each pin of FPGA in kernel space;

[0085] Step 83, open the file that deposits the configuration data of FPGA in operating system;

[0086] Step 84, if there is an error in opening the file, abnormal processing is performed, for example, if the file fails to open, the file can be reopened, and if it fails to open a...

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Abstract

The invention discloses an FPGA configuration method, an FPGA configuration system and a processor. The FPGA configuration method includes that the processor pulls an electrical level of a PROGRAM_B base pin from a high level down to a low level, and pulls the electrical level of the PROGRAM_B base pin from the low level up to the high level after the low level is maintained for a preset period; if the result that an electrical level of an INIT_B base pin is pulled from the low level to the high level is detected, an SCLK base pin sends a synchronous clock signal of an SPI bus to an FPGA, and an MOSI base pin sends configuration data to the FPGA; completion of configuration for the FPGA is confirmed after the result that an electrical level of a DONE base pin is pulled from the low level up to the high level is detected. The FPGA configuration method, the FPGA configuration system and the processor solve the problems that synchronous clock rate simulated by the processor is low and transmission rate of configuration data is low when the FPGA is configured, and accordingly consuming time of FPGA configuration is long, and quick start of the FPGA configuration system is restricted in the prior art.

Description

technical field [0001] The invention relates to the field of communication technology, in particular to an FPGA configuration method, system and processor. Background technique [0002] Field Programmable Gate Array (FPGA, Field Programmable Gates Array) is a high-density field programmable logic device. Memory) to achieve. FPGA has reprogrammability and can flexibly implement various logic functions. [0003] FPGAs based on SRAM technology are volatile. After the FPGA chip is powered off, the configuration data in the SRAM is easy to lose, so an external read-only memory (ROM, Read-Only Memory) is needed to save its configuration data, then after the chip is powered on, it is necessary to reconfigure the FPGA, that is, to Load configuration data into the FPGA. [0004] In the prior art, FPGA configuration methods are flexible and diverse. Depending on whether the FPGA chip can actively load configuration data, the FPGA configuration methods can be divided into a master ...

Claims

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Application Information

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IPC IPC(8): G06F13/20
Inventor 凌兴锋黄健安
Owner COMBA TELECOM SYST CHINA LTD