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Device for calculating adjoint polynomial in RS encoder

A technology with polynomials and computing devices, applied in cyclic codes, using linear codes for error correction/detection, using block codes for error correction/detection, etc., can solve problems such as high energy consumption, achieve low energy consumption, and reduce the number of clock cycles , easy-to-achieve effects

Inactive Publication Date: 2014-07-16
PEKING UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Typically, the deinterleaver needs to run at high speed and results in high power consumption

Method used

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  • Device for calculating adjoint polynomial in RS encoder
  • Device for calculating adjoint polynomial in RS encoder
  • Device for calculating adjoint polynomial in RS encoder

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Embodiment Construction

[0037] In order to make the method and advantages of the present invention clearer and easier to understand, the device for calculating the adjoint polynomial in the RS coder provided by the present invention will be described in detail below in conjunction with the accompanying drawings, but this does not constitute a limitation to the present invention.

[0038] figure 1 It is a schematic diagram of the basic unit used in the accompanying computing device disclosed in the present invention. Such as figure 1 As shown, the basic unit of the adjoint computing device disclosed in the present invention includes data input ports 1-4, Galois field constant multipliers 5-7 and 17,

[0039] Galois field adder 21, multiplexer and demultiplexer 13, 19 and 8, mode selection signal 8, 13, sync signal 18 and several registers. The "registers" mentioned in the present invention all refer to a register set with a certain bit width, and the bit width depends on the m value of the selected ...

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Abstract

The invention discloses a device for calculating an adjoint polynomial in an RS encoder. The device has the smaller adjoint calculation delay and the higher encoding rate, and meanwhile the device does not need to be provided with a front-arrangement de-interleave device. In order to achieve the aim, the invention discloses a method for enabling an adjoint calculation device to support the multichannel parallel input through the adjoint calculation formula conversion. The adjoint calculation device comprises a multichannel parallel data input interface and 2t basic units. Each basic unit comprises a plurality of Galois field constant multipliers connected with the multichannel parallel input, a Galois field summator, a Galois field constant multiplier, a plurality of registers, a plurality of multiplexers and a plurality of demultiplexers, wherein the Galois field constant multiplier is connected with the registers.

Description

technical field [0001] The invention relates to the technical field of digital communication channel coding, in particular to a multi-channel parallel adjoint computing device used for an RS code decoder. Background technique [0002] During the transmission process, the digital signal will be distorted by the interference of various channel noises. After receiving the distorted signal, there is a certain probability that the receiving end will make a wrong decision, that is, a bit error. In order to make the data communication efficient and correct, Error control techniques are required. Among them, the forward error correction technology enables the receiving end to use the error control symbols added by the sending end in the symbol sequence, not only to find the error code but also to restore the error code to its correct value. At the same time, the forward error correction technology does not need the reverse channel to transmit instructions, and there is no time dela...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/15H04L1/00
Inventor 郭文盖伟新
Owner PEKING UNIV
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