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An output buffer, gate drive circuit and control method thereof

A gate drive circuit and output buffer technology, applied in logic circuits, logic circuit connection/interface layout, instruments, etc., can solve the problems of large conduction current, large specific gravity, and large short-circuit current power consumption

Active Publication Date: 2017-10-24
BOE TECH GRP CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, when the width-to-length ratio of the device is large, the conduction current will also become large, resulting in a large corresponding short-circuit current power consumption, and a large proportion in the overall power consumption.

Method used

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  • An output buffer, gate drive circuit and control method thereof
  • An output buffer, gate drive circuit and control method thereof
  • An output buffer, gate drive circuit and control method thereof

Examples

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Embodiment 1

[0036] Embodiment 1 of the present invention provides an output buffer, the composition diagram is as follows image 3 As shown, it includes a first transistor 10 and a second transistor 20, and also includes an input signal control unit 30 to control the input signal IN to obtain a pull-up signal PU and a pull-down signal PL, which are respectively connected to the first transistor 10 and the second transistor 20 inputs.

[0037] Preferably, the input signal control unit 30 in this embodiment includes an input signal IN and at least two control signals.

[0038] Preferably, the input signal control unit 30 in this embodiment further includes at least two NAND gates, the input terminals of the NAND gates are the control signal and at least one input signal IN, and the output terminals are respectively the pull-up of the input terminal of the first transistor 10 The signal PU and the pull-down signal PL of the second transistor 20 .

[0039]Preferably, the input signal contro...

Embodiment 2

[0046] Based on the output buffer in the first embodiment above, the second embodiment of the present invention also provides a gate drive circuit, the schematic diagram of which is shown in Figure 5 shown, including:

[0047] The output buffer 110 and the input signal generation unit 120 , the input signal generation unit 120 is used to generate the input signal IN of the output buffer 110 , and the output terminal of the output buffer 110 outputs a gate signal Gate.

[0048] Preferably, the input signal generation unit 120 includes a clock signal CLK, an input start signal STV and a generation module 100, the input of the generation module 100 is connected to the clock signal CLK and the input start signal STV, and the lock is realized under the control of the clock signal CLK Store and shift and generate an input signal IN, which is output from the output terminal of the generating module 100 .

[0049] Preferably, the generating module includes two inverters and two tri-...

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Abstract

The present disclosure discloses an output buffer, a gate electrode driving circuit and a method for controlling the same. The output buffer includes a first transistor, a second transistor and an input signal control unit. The input signal control unit controls an input signal to obtain a pull-up signal and a pull-down signal, which are input to input terminals of the first transistor and the second transistor, respectively. The above output buffer uses the input signal control unit to divide one input signal into two signals, i.e., the pull-up signal and the pull-down signal.

Description

technical field [0001] The invention relates to the technical field of liquid crystal display, in particular to an output buffer, a gate drive circuit and a control method thereof. Background technique [0002] In digital integrated circuits, buffers are generally divided into two types: input buffers and output buffers. The input buffer temporarily stores the data sent by the peripheral so that the processor can take it away; the output buffer is used to temporarily store the data sent by the processor to the peripheral. [0003] The connection diagram of the commonly used output buffer is as follows: figure 1 As shown, the CMOS buffer is composed of an even number of inverters, and the device size of each stage is enlarged to improve the driving load capability of the buffer. The output P of the input signal IN and CK after passing through the two-input NAND gate is used as the input of the output buffer, and the output buffer includes two transistors, the first transist...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/0175G09G3/36
CPCH03K19/0948H03K19/09429
Inventor 祁小敬胡理科
Owner BOE TECH GRP CO LTD
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