Shift temporary storage circuit and shift register

Abstract

The invention discloses a shift temporary storage circuit comprising a plurality of shift registers. Each shift register comprises at least four input ends, a pull-up circuit, a first switch, a first pull-down circuit and a second pull-down circuit. A control end of the first switch is coupled to a node. The pull-up circuit is used for pulling up the electric potential of the node. The first pull-down circuit is used for pulling down the electric potential of the shift register. The second pull-down circuit is used for pulling down the electric potential of the node. The abovementioned four input ends are connected with different clock rate signals respectively to prevent surge at the node caused by a coupling effect of stray capacitance of the first switch, so that the positive bias stress effect caused by two transistors of the first pull-down circuit and the second pull-down circuit is prevented.

Description

technical field [0001] The present invention relates to a shift register circuit and a shift register, in particular to a shift register capable of alleviating the coupling effect (coupling effect) and positive bias stress (positive bias stress; PBS) effect of transistor parasitic capacitance. Temporary storage circuit and shift register. Background technique [0002] Generally speaking, a display panel includes a plurality of pixels, a gate driving circuit and a source driving circuit. The gate driving circuit includes a multi-level shift register for providing multiple gate driving signals to control the on and off of the pixels. The source driving circuit is used for writing data signals to the turned-on pixels. In addition, the current display panel often adopts a gate driver on array (GOA) technology to provide the gate driving signal required by the pixels. Different from the traditional gate driver, the circuit using GOA can reduce the production cost of the panel ...

AI Technical Summary

Problems solved by technology

[0007] However, due to the coupling effect of the parasitic capacitor of the switch T1b, the input signal G output from the output terminal of the previous stage shift register N-1 Before the gate low potential VGL is pulled up to the gate high potential VGH again, since the potential of the clock signal CK is still switched between the gate high potential VGH and the gate low potential VGL, it is easy to switch between the gate high potential VGH and the gate low potential VGL. Q N A glitch is generated, which in turn leads to the output signal G of the shift register 100 N The waveform of the

In addition, since the switches T1c and T1d use the low gate potential VGL as their low-level signal, the switches T1c and T1d are prone to produce positive bias stress (positive bias stress; PBS) effect, so that the switches T1c and T1d can be used for a long time. After operation, its critical voltage will have a positive shift, resulting in a decrease in the drive capability of switches T1c and T1d

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