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Semiconductor device with P top layer and N energy level and manufacturing method of semiconductor device

A semiconductor and energy level technology, applied in metal oxide semiconductor devices, in the field of manufacturing this device, can solve the problem of high on-resistance

Active Publication Date: 2014-08-06
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, due to the mutual influence between the N-level region and the P-type fully doped region, the dedicated on-resistance of known high-voltage LDMOS is still too high

Method used

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  • Semiconductor device with P top layer and N energy level and manufacturing method of semiconductor device
  • Semiconductor device with P top layer and N energy level and manufacturing method of semiconductor device
  • Semiconductor device with P top layer and N energy level and manufacturing method of semiconductor device

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Embodiment Construction

[0133] Certain embodiments of the invention will now be fully described below with reference to the accompanying drawings, but not all embodiments of the invention will be shown, various embodiments of the invention may be embodied in many different forms, and should not be construed as Rather, these examples are provided so that this invention will satisfy applicable legal regulations.

[0134] Unless the context clearly indicates otherwise, the singular forms "a" and "the" used in the description of this case and the appended claims shall cover multiple references, for example, the reference to "a PIM section" includes multiple references such a Ptop segment.

[0135] Certain specific terms used in the present invention are used in general and descriptive terms only and not for the purpose of limitation. All terms, including technical and scientific terms, unless the context clearly defines otherwise, have the same meaning as in the present invention. the same meaning as co...

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PUM

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Abstract

The invention discloses a semiconductor device with a P top layer and an N energy level. The semiconductor device comprises a P substrate, a high-voltage N well, a first P well, a second P well and a separated N energy level and P top region, the high-voltage N well is arranged in the P substrate, the first P well is formed in the P substrate with a first P+ doped region, the second P well is formed in the high-voltage N well (HVNW) with a second P+ doped region, the second P+ doped region is adjacent to an N+ doped source region, the separated N energy level and P top region is arranged in the HVNW and provided one or more layers defined by multiple P top zones and distributed among multiple N energy level zones, and the N energy level and the P top layer are defined by N-type and P-type diffusion zones arranged separately in sequence. The invention further provides a manufacturing method of the semiconductor device.

Description

technical field [0001] Embodiments of the present invention relate to a semiconductor device, particularly a metal oxide semiconductor device, and a method of manufacturing the device. Background technique [0002] Diffuse metal-oxide-semiconductor (DMOS) devices are characterized by simultaneously diffused source and gate-last regions. The transistor channel is formed by a difference in the two diffusions and not a separate implant, which results in a shortened channel length. Shorter channels allow low power consumption and high speed capability. [0003] A laterally diffused metal-oxide-semiconductor (LDMOS) device has sources and drains on its wafer surface that cause lateral current flow. Two important parameters for designing LDMOS devices are breakdown voltage and on-resistance. Preferably, the high breakdown voltage and low on-resistance allow the device to have relatively low power consumption under high voltage operation. In addition, the low on-resistance prov...

Claims

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Application Information

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IPC IPC(8): H01L29/78H01L29/06H01L29/739H01L29/861H01L21/336H01L21/331H01L21/329
CPCH01L29/0619H01L29/66325H01L29/66681H01L29/7393H01L29/7816
Inventor 詹景琳林镇元林正基连士进
Owner MACRONIX INT CO LTD