Double gate field effect transistor with tensile strain film strain source and its preparation method

Abstract

The invention provides a double-gate field effect transistor with a tension strain thin film strain source and a preparation method of the double-gate field effect transistor with the tension strain thin film strain source. The double-gate field effect transistor comprises a semiconductor material, a gate dielectric layer, a grid electrode, a tension strain thin film strain layer, a source region electrode and a drain region electrode. The tension strain thin film strain layer is formed on an insulating dielectric layer and used for leading tension strain in the channel direction into a conducting channel region. The surface of the double-gate field effect transistor is covered with the tension strain thin film strain layer, a tension strain thin film swells to lead the large tension strain in the channel direction into the conducting channel region in the preparation process, and then double-axis tension strain is led into a source channel interface and a nearby region; the strain is beneficial to drop of a gamma point of a GeSn conduction band of a channel, and an indirect band gap is converted into a direct band gap, so that the current is increased, the working current of the double-gate field effect transistor is increased, and on-resistance is lowered.

Description

technical field [0001] The invention relates to the technical field of semiconductor design and manufacture, in particular to a double-gate field-effect transistor with a tensile strain film strain source and a preparation method thereof. Background technique [0002] With the in-depth development of integrated circuit technology, the improvement of wafer size and the reduction of chip feature size can meet the requirements of miniaturization, high density, high speed, high reliability and system integration. According to the forecast of the International Technology Roadmap for Semiconductors (ITRS), when the technology node of integrated circuits reaches below 10 nanometers, strained Si materials can no longer meet the needs, and high carrier mobility materials must be introduced to improve chip performance. . [0003] Theory and experiments show that GeSn has higher carrier mobility than pure Ge materials. Theoretical calculations show that by adjusting the Sn compositio...

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Problems solved by technology

However, as the Sn composition increases, the material quality and thermal stability will deteriorate, so it is difficult to realize the direct bandgap GeSn material simply by increasing the Sn composition.

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