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Dual mode insulation gate transistor
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An insulated gate transistor, dual-mode technology, applied to semiconductor devices, electrical components, circuits, etc., can solve the problems of large size of the guide area and current concentration in the area near the guide area, and achieve uniform distribution, reduce turn-on voltage, and improve reliability Effect
Active Publication Date: 2014-09-10
JIANGSU CAS IGBT TECHNOLOGY CO LTD
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[0009] The technical problem to be solved by the present invention is to provide a dual-mode insulated gate transistor, which solves the technical problem that the size of the guide region of the dual-mode insulated gate transistor in the prior art is too large, resulting in serious current concentration in the guide region and its vicinity
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Embodiment 1
[0038] see figure 1 , figure 2 , image 3 and Figure 4 , in this embodiment, the guide area includes a separation area, and the basic idea is to separate the N+ buffer layer of the guide area from the N+ buffer layer of the reverse guide area, which means to isolate the two parts of the buffer layer structure from each other, such as figure 1 and figure 2 shown. The separation region is a semiconductor substrate that is not doped into the buffer layer, and generally has the same doping concentration as the N-drift region. Of course, a small amount of impurities can also be appropriately introduced or this region can be processed into a semiconductor structure with a resistivity greater than that of the N-drift region.
[0039] In order to ensure the withstand voltage of the device, an insulator region of a certain size is manufactured under the separation region, and the insulator region is located between the semiconductor substrate and the collector metal layer. The ...
Embodiment 2
[0043] The structure of the dual-mode insulated gate transistor provided by this embodiment is similar to that of Embodiment 1. The difference between the two is that the separation region of embodiment 2 is a trench filled with an insulator, and the N+ buffer layer and the collector region are separated by a trench filled with an insulator (such as Figure 5 and Image 6 ). The buffer layer on the left side of the groove shown in the figure is the buffer layer of the guide area, and the buffer layer on the right side of the groove is the buffer layer of the reverse guide area.
[0044] In this embodiment, a section of P+ collector region (such as Figure 5 ), can also be directly set as N+ collector area (such as Image 6 ).
[0045] When the device is in VDMOS mode, the electron current above the guide region must flow through the buffer layer of the guide region (the distribution resistance is Rb1), the low doped regions on both sides and above the trench (the total dis...
Embodiment 3
[0047] In fact, not only the dual-mode insulated gate transistor with FS structure can adopt this solution, but also the dual-mode insulated gate transistor with NPT structure can improve the current uniformity. The structure of the reverse conduction region proposed in Example 3 is similar to that in Example 2. The difference between the two is that there is no N+ buffer layer structure in the structure of Example 3.
[0048] In this embodiment, a section of P+ collector region (such as Figure 7 ), can also be directly set as N+ collector area (such as Figure 8 ).
[0049] When the device is in VDMOS mode, the electron current above the guide region must flow through the drift region of the guide region (the distribution resistance is Rd1), the low-doped regions on both sides and above the trench (the total distribution resistance is Rd) and the reverse conduction region The drift region above the N+ collector region (distributed resistance is Rd2). The introduction of ...
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Abstract
The invention discloses a dual mode insulation gate transistor, and belongs to the technical field of IGBT (insulated gate bipolar transistors). The dual mode insulation gate transistor comprises a reverse conducting sector and a boot sector, wherein the reverse conducting sector and the boot sector both comprise P+ collector regions, drift regions and MOS cellular regions, the drift regions are respectively located above the P+ collector regions, the MOS cellular regions are respectively located above the drift regions, the reverse conducting sector further comprises N+ collector regions, the N+ collector regions and the P+ collector regions are alternatively distributed, the boot sector further comprises a separation region or a low adulteration region, the separation region insulates the P+ collector region of the boot sector from the P+ collector region and the N+ collector region of the reverse conducting sector, and the low adulteration region is located above the P+ collector region of the boot sector. According to the dual mode insulation gate transistor, the size of the boot sector of the dual mode insulation gate transistor is decreased by increasing resistance of an electron current channel above the boot sector or built-in potential of a collector PN junction of the boot sector when devices are in VDMOS mode, and therefore uniformity of the internal electric current density when the devices work is improved, and then overall reliability of the devices is improved.
Description
technical field [0001] The invention belongs to the technical field of IGBTs, in particular to a dual-mode insulated gate transistor. Background technique [0002] RC-IGBT introduces an N+ doped region (N+ collector region) into the back collector region of the traditional IGBT, thereby adding a reverse current channel to the device. RC-IGBT has advantages in cost and performance, and can replace traditional IGBT in some fields. The biggest problem with RC-IGBT is that the voltage will have snap-back (hereinafter referred to as "bounce") when it is turned on, which greatly limits the application of the device. In order to suppress the bounce phenomenon, RC-IGBT usually needs to ensure that the distance between adjacent N+ collector regions is large enough, but this also causes uneven current distribution inside the chip and affects the reliability of the device. For this reason, a BIGT (dual-mode insulated gate transistor) structure is proposed, which integrates the RC-IGB...
Claims
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Application Information
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