Router Fault Tolerance Method Based on Fault Channel Isolation Detection in Network-on-Chip

An on-chip network and router technology, applied in the field of router fault tolerance based on fault channel isolation and detection, can solve problems such as area and power consumption overhead, and achieve the effects of reducing complexity, reducing fault tolerance overhead, and reducing overhead

Active Publication Date: 2018-02-23
黄山市开发投资集团有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Redundancy reinforcement is performed on the entire router, so that the reliability of the circuit must be guaranteed, but the area and power consumption overhead caused by the use of multi-mode redundancy for large components is unacceptable for general networks

Method used

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  • Router Fault Tolerance Method Based on Fault Channel Isolation Detection in Network-on-Chip
  • Router Fault Tolerance Method Based on Fault Channel Isolation Detection in Network-on-Chip
  • Router Fault Tolerance Method Based on Fault Channel Isolation Detection in Network-on-Chip

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Embodiment Construction

[0035] A router fault-tolerant method based on fault channel isolation detection in a network on chip, the operation steps are as follows:

[0036] a. When a data packet transmission request arrives, query the fault channel vector table to find out the corresponding fault state of the request channel. If the request channel is not faulty, the data packet will be transmitted to the output port through the request channel. If the request channel has a permanent failure, then the The data packet turns to request the redundant channel, and then is transmitted to the output port by the redundant channel;

[0037] b. After the data packet arrives at the output port, ECC detection is performed. If there is no error in the data bit, the data is transmitted normally. If there is a single error in the data bit, it will be automatically corrected and then transmitted. c;

[0038] c. If there is a multi-bit error in the data bit, notify the upstream router to retransmit the data in the f...

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Abstract

The invention discloses that the invention proposes a router fault tolerance method based on fault channel isolation detection in a network-on-chip. The fault channel isolation detection technology is used to detect the channel fault in the router, so that the fault detection does not affect the normal data transmission; The Buffer is used to temporarily store the transmitted data for retransmission of erroneous data in the faulty channel to reduce the fault tolerance overhead of the router; at the same time, a redundant channel is added to transmit the data in the permanently faulty channel. The invention realizes normal data transmission while detecting faults at the expense of less hardware overhead, reduces network delay and improves network throughput.

Description

technical field [0001] The invention relates to the technical field of fault-tolerant integrated circuit chip design, in particular to a router fault-tolerant method based on fault channel isolation detection in an on-chip network. Background technique [0002] Network-on-Chip (NoC, Network-on-Chip) provides efficient communication between different cores of a multiprocessor system-on-chip. Compared with a bus-based system-on-chip (SoC, System-on-Chip), it has high The advantages of delay and scalability. A typical on-chip network system is composed of routers, communication links and resource nodes (processor units or IP cores, etc.). [0003] However, with the continuous reduction of the size of the transistor industry and the gradual increase of the network scale, circuit unreliability problems caused by process instability, manufacturing process variation and degradation, electromigration, etc. are becoming more and more serious. It is an indispensable branch in the st...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/24H04L1/18H04L12/771H04L45/60
Inventor 欧阳一鸣陈义军黄正峰梁华国汪秀敏易茂祥陈田安鑫
Owner 黄山市开发投资集团有限公司
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