Array substrate, display device and manufacture method of the array substrate

Abstract

The invention discloses an array substrate, a display device and a manufacture method of the array substrate. The array substrate comprises an IC crimping region including an IC region and a terminal region arranged on one side of the IC region and near an edge of the array substrate. The terminal region is provided with a plurality of transmission terminals. The IC region comprises a conductor layer, a first insulating layer, a separating layer and a second insulating layer stacked one by one. Each transmission terminal comprises a first conductive layer which is arranged on the second insulating layer and extends from the terminal region to the IC region. The separating layer is arranged in the IC region and at least overlaps with the first conductive layers extending to the IC region. When a small-size IC chip is adopted, contact failure between the IC chip and the terminals of the array substrate can be prevented. Meanwhile, short circuit risks between the first conductive layers and the conductor layer can be avoided.

Description

technical field [0001] The invention relates to flat panel display technology, in particular to an array substrate, a display device and a manufacturing method of the array substrate. Background technique [0002] Flat panel display devices have the advantages of thinness, low power consumption, and low radiation, and are widely used in various fields. With the rapid development of science and technology, people have higher and higher quality requirements for flat panel display devices. Wide viewing angles, ultra-thin, and narrow bezels have gradually become important factors for selecting flat panel display devices. [0003] COG packaging (chip on glass) is a packaging technology that directly binds the driver chip on the glass. This method can greatly reduce the volume of the entire flat panel display device and reduce the number of wiring and layers on the printed circuit board. , reducing board size and complexity, reducing overall cost. [0004] figure 1 It is a stru...

AI Technical Summary

Problems solved by technology

However, under the premise that the design structure of the array substrate remains unchanged, if the IC chip is too small, when the IC chip is bound, the output pin of the IC chip should be matched with the output terminal first. At this time, the input pin of the IC chip will Entering the routing area of ​​the IC chip placement area, the contact area between the IC chip terminal pins and the input terminals on the array substrate will become smaller, resulting in poor contact between the IC chip and the array substrate terminals. will also increase

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