Capless LDO (Low Dropout Regulator)

Abstract

The invention relates to the technical field of electronic circuit engineering, and particularly relates to a capless LDO (Low Dropout Regulator). The capless LDO comprises a PMOS (P-channel Metal Oxide Semiconductor) pipe MP (Melting Point), a capacitor C2, a resistor R2, a buffer, an error amplifier and a dynamic transconductance intensifier circuit, wherein the in-phase input end of the buffer is connected with an external reference voltage Vref, and the inverted input end of the buffer is connected with the output end of the buffer connected with the inverted input end of the error amplifier; the in-phase input end of the error amplifier is connected with the output end of the LDO, and the output end of the error amplifier is connected with the output end of the dynamic transconductance intensifier circuit; the first bias end VB1 of the dynamic transconductance intensifier circuit is connected with the first bias end of the error amplifier, and the second bias end VB2 of the dynamic transconductance intensifier circuit is connected with the second bias end of the error amplifier, and the output end of the dynamic transconductance intensifier circuit is connected with the grid of the MP. The capless LDO provided by the invention has the beneficial effects of improving the transient state response of the LDO in a SoC (System on a Chip) application, and the external current can be provided by a DTE (Data Terminal Equipment). The capless LDO is particularly applicable to the LDO.

Description

technical field [0001] The invention belongs to the technical field of electronic circuits, and in particular relates to a capacitorless low dropout linear regulator (LDO, Low Dropout Regulator). Background technique [0002] Complex SoC (System on Chip) requires multi-voltage and low-noise power supply, and integrating the entire power management system is conducive to simplifying the layout and wiring of the power network and saving system costs. Low-dropout linear regulator is an important research field of power management integrated circuits. The attenuation of high-frequency power supply suppression and load transient response performance is the main problem in the integration process. It is expected to adopt new technologies to make breakthroughs. [0003] In order to obtain an output voltage with fast transient response and low noise, an on-chip capless LDO needs to be integrated into the SoC system. No need for bulky off-chip capacitors saves pin count and board sp...

AI Technical Summary

Problems solved by technology

The traditional slew rate enhancement circuit is non-linear and easy to oscillate

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