A semiconductor packaging substrate structure and manufacturing method thereof
A technology for packaging substrates and manufacturing methods, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., and can solve problems such as poor physical and chemical properties, poor reliability, and low optical resolution
Active Publication Date: 2017-11-14
NAT CENT FOR ADVANCED PACKAGING CO LTD
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- Application Information
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Problems solved by technology
After making the outermost circuit, print solder mask (Solder Mask) to form solder pads through exposure, development and other processes. The production of solder mask ink in the conventional process is caused by the low optical resolution and poor physical and chemical properties of the solder mask material. Problems such as large substrate pad spacing and poor reliability
Method used
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[0034] The invention will be described in detail below in conjunction with the accompanying drawings, but this embodiment is not limited to the present invention, and the structural, method or functional transformations made by those of ordinary skill in the art according to this embodiment are included in the scope of the present invention. within the scope of protection.
[0035] See figure 1 , a semiconductor packaging substrate structure, which includes a core board (Core Layer) 101, a build-up layer (Build-up Layer) 102 is arranged on both sides of the core board 101, and the build-up layer (Build-up Layer) 102 and the core board 101 They are connected through blind vias (Blind Via) 105, the bottom of the blind vias 105 is connected to the pad 109 of the line surface build-up layer, the blind vias 105 are provided with a plug material, and the upper and lower sides of the core board 101 are built-up layers (Build-up Layer) 102 is provided with a conductive line 103, the...
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The invention provides a semiconductor packaging substrate structure. The reliability of a substrate bonding pad is guaranteed while the distance of the substrate bonding pad is effectively decreased. The semiconductor packaging substrate structure comprises a core plate and is characterized in that storey-addition layers are arranged on the two sides of the core plate and connected with the core plate through blind holes, the bottoms of the blind holes are connected with bonding pads of the line face storey-addition layers, conducting circuits are arranged on the storey-addition layers or inside the storey-addition layers, through holes are formed in the core plate, the conducting circuits on the upper face and the lower face of the core plate are connected through the through holes, hole plugging materials are arranged in the through holes, metal columns are arranged in the storey-addition layers on the upper face and the lower face, and the metal columns are arranged in the storey-addition layers and connected with an inner-layer conducting layer. The invention further provides a manufacturing method of the semiconductor packaging substrate structure.
Description
technical field [0001] The invention relates to the technical field of microelectronic packaging technology, in particular to a semiconductor packaging substrate structure and a manufacturing method thereof. Background technique [0002] With the development of semiconductor technology, Moore's Law is approaching the edge of failure. The difficulty of IC design, wafer manufacturing, packaging and testing in the industry chain continues to increase. The pitch of the chip pads keeps getting smaller, and the development of the pitch of the undercut pads of the package substrate cannot keep up with the pace of changes in the pitch of the chip pads. How to reduce the pad pitch of the packaging substrate has become an urgent problem to be solved. [0003] A build-up process is used in the manufacturing process of the existing package substrate. After making the outermost circuit, print solder mask (Solder Mask) to form solder pads through exposure, development and other process...
Claims
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IPC IPC(8): H01L23/31H01L21/56
Inventor 陈峰
Owner NAT CENT FOR ADVANCED PACKAGING CO LTD