A dram with memory controller

Abstract

The invention discloses a DRAM with a storage controller, the external data bus is connected with the system data line, and the inside is connected with the ECC inspection and error correction module, and the ECC inspection and error correction module is further connected with the data line of the main data DRAM module The ECC check and error correction module completes the ECC encoding of the written data and the ECC decoding of the read data; the DRAM parameter storage module is internally connected with the address remapping module, and the DRAM parameter storage module passes independent data The interface is connected with the system; the external address bus is connected externally with the system address line, and internally connected with the address remapping module, then the delay module, and finally connected with the address line of the internal DRAM; the external command bus is first connected with the delay module connected, and then connected to the command bus of the internal main data DRAM. By adding the ECC check, error correction module and address remapping module, the DRAM connected to the address remapping module is used to store the ECC check and error correction information, which reduces the defect rate of the DRAM as a whole.

Description

technical field [0001] The invention relates to the field of information storage, in particular to a high-reliability DRAM with a new storage controller. Background technique [0002] The development of the DRAM manufacturing process reduces the cost of a unit cell (memory unit), while the reliability of the DRAM itself is getting worse. At present, the DRAM process technology has developed to the 2X nm era, and the follow-up will continue to think about the development of 1X nm or even smaller process technology. As the manufacturing process becomes smaller and smaller, the reliability of DRAM cells will become lower and lower; in the production process of DRAM, the probability of bad cells due to impurity pollution and other reasons is also increasing. This will lead to the DRAM redundancy and replacement methods currently in use are no longer sustainable, because the complexity will be too high and the cost will not be acceptable. [0003] In the current DRAM redundancy...

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