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Design method for non-real time clock

A design method and non-real-time technology, applied in the field of storage, can solve the problems of high power consumption and long calculation cycle, etc., and achieve the effect of reducing energy consumption and improving the computing power of the system

Active Publication Date: 2014-12-03
SHANGHAI XINCHU INTEGRATED CIRCUIT
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, there are certain defects in the clock design, the calculation cycle is longer, and the power consumption is still relatively high.

Method used

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  • Design method for non-real time clock
  • Design method for non-real time clock

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Embodiment Construction

[0029] In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.

[0030] It should be understood that the invention can be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

[0031] The terminology used herein is for the purpose of describing part...

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Abstract

The invention provides a design method for a non-real time clock. The design method for the non-real time clock comprises the following steps: benchmark modules in different grades are arranged on a chip; each grade of benchmark module outputs reference signals of which the signal intensity is gradually increased or diminished; a storage unit with a floating gate structure is arranged on the chip; the electrical current (or the electric pressure ) of the storage unit is read and the electrical current ( or the electric pressure ) of the storage unit is compared with the reference signals; according to the results of the comparison, the time of the non-real time clock is judged; therefore, corresponding operations are conducted; the power consumption is lowered and the processing performance of the system is lifted.

Description

technical field [0001] The invention relates to the technical field of storage, in particular to a design method of a non-real-time clock. Background technique [0002] NAND solid-state drives (SSDs) have become the mainstream non-volatile storage technology and are widely used in various fields such as data centers, personal computers, mobile phones, smart terminals, and consumer electronics, and the demand is still growing. [0003] The NAND storage unit stores a lot of data, the structure is relatively complex, the probability of error will increase, and more error correction (ECC, Error Correction Code) must be carried out. Some NAND units with poor data retention capabilities even need to be periodically refreshed. To ensure data reliability, in order to ensure the safety and accuracy of users' data in solid-state drives, regular active testing is required in solid-state drives. For example, which NAND chip needs to be refreshed (refresh), which NAND chip needs wear le...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F1/32
Inventor 景蔚亮陈邦明
Owner SHANGHAI XINCHU INTEGRATED CIRCUIT
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