Complementary cascode inverter and incremental sigma-delta analog-to-digital conversion circuit
An analog-to-digital conversion circuit, cascode technology, applied in delta modulation and other directions, which can solve problems such as gain and bandwidth limitation, DC operating point and strong process sensitivity of inverters
Active Publication Date: 2017-11-21
HARBIN ENG UNIV
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However, two important problems with this method are: the gain and bandwidth are severely limited; since the inverter has no virtual point, it needs to be self-established, resulting in extremely strong process sensitivity for the DC operating point and the AC characteristics of the inverter
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[0022] The specific implementation manners of the present invention will be described below in conjunction with the accompanying drawings.
[0023] The present invention is composed of a second-order delta ΣΔ modulator section 101 , a downsampling filter section 102 , a clock signal generation circuit 103 , and a low voltage-high voltage converter 104 . The second-order incremental ΣΔ modulator 101 converts the input DC voltage into a 1-bit digital quantity containing high-frequency quantization noise, and the 1-bit digital quantity is input to the down-sampling filter 102, and converted into an N-bit digital output, and the clock signal is generated A part of the clock signal generated by the circuit 103 is sent to the second-order delta ΣΔ modulator 101 through the low-voltage-high-voltage converter 104 , and the other part is sent to the down-sampling filter unit 102 .
[0024]The second-order delta ΣΔ modulator part 101 is the core circuit of the whole system, which determ...
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The invention provides a complementation common-source common-grid inverter and an increment Sigma-Delta analog-to-digital conversion circuit. The increment Sigma-Delta analog-to-digital conversion circuit is composed of a second-order sigma delta modulator (101), a reduction sampling filter (102), a clock signal generation circuit (103) and a low-to-high voltage converter (104). A switch capacitance integrator at the band reset end of the second-order sigma delta modulator (101) comprises the complementation common-source common-grid inverter. The complementation common-source common-grid inverter comprises a first PMOS1 tube and a first NMOS1 tube. A second NMOS2 tube and a second PMOS2 tube are connected in series between the first PMOS1 tube and the first NMOS1, the second NMOS2 tube is arranged at an upper position, the grid end of the second NMOS2 tube is connected with a power supply voltage VDD, the second PMOS2 tube is disposed at a lower position, and the grid end of the second PMOS2 tube is grounded GND. The ADC provided by the invention has quite low power consumption and can work under the condition of low power supply voltage, thereby being applied to such fields of a portable instrument, measuring, and the like.
Description
technical field [0001] The invention relates to a low-voltage and low-power incremental ΣΔ analog-to-digital converter. Background technique [0002] Sigma-Delta (ΣΔ) analog-to-digital converter (ADC) is widely used in communication and multimedia fields due to its simple structure, low power consumption, high precision and no need for device matching. However, the traditional ΣΔ structure is not suitable for instrumentation and measurement applications, where very high accuracy and linearity are required, and very low offset and gain errors are required in addition to high dynamic range and signal-to-noise ratio. Traditional ΣΔ ADCs only focus on dynamic characteristics such as signal-to-noise ratio and effective bits. Incremental ΣΔ ADCs are ideal for instrumentation and measurement applications because they provide low offset, low gain error, point-to-point, high-precision analog-to-digital conversion with relatively short conversion times. [0003] In areas such as ins...
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IPC IPC(8): H03M3/02
Inventor 刘云涛邵雷高松松
Owner HARBIN ENG UNIV