Resource distribution method for reconfigurable chip multiprocessor with task number and performance sensing functions

A multi-core processor and resource allocation technology, applied in the direction of resource allocation, multi-programming devices, etc., can solve the problems of reduced efficiency, achieve the effect of reducing the average turnaround time, improving system throughput and chip resource utilization

Active Publication Date: 2015-02-04
UNIV OF SCI & TECH OF CHINA
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If the efficiency of the task is greater than the maximum efficiency, it means that the logical core occupied by

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  • Resource distribution method for reconfigurable chip multiprocessor with task number and performance sensing functions
  • Resource distribution method for reconfigurable chip multiprocessor with task number and performance sensing functions

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[0045] The purpose, advantages and key technologies of the present invention will be explained through the following specific implementation methods. This implementation is only a typical example of the solution, and any technical solution formed by replacement or equivalent transformation falls within the scope of protection claimed by the present invention. This section applies the invention to support dynamic resource allocation on a typical DRCMP structure (TFlex).

[0046] In the TFlex structure, there are a total of 32 physical cores on the chip, and the maximum number of tasks that can run simultaneously is 16. There are 1, 2, 4, 8, and 16 logical cores in total, namely logical cores composed of 1, 2, 4, 8, and 16 physical cores. During the task jittering stage or the performance information collection stage of the system, the logic cores are evaluation-type, and their number and granularity depend on the number of concurrently running tasks. If the number of tasks ru...

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Abstract

The invention relates to a resource distribution method for a reconfigurable chip multiprocessor with task number and performance sensing functions. The dynamic reconfigurable chip multiprocessor has the capability of dynamically reconfiguring on-chip resources during running, so as to reduce the task average turnover time, improve the system throughput rate and the chip resource utilization rate, and provide a large optimization space. The method has the advantages that in each dispatching interval of an operation system, a resource allocator is used for firstly averagely allocating a logic core according to the task number, sequencing the tasks according to the performances (for reflecting the requirement of the task on the resource) after running for a certain clock cycle, finding the task with small demand on resource, reducing the granularity of the occupied logic core, and allocating the vacant physical core from the task with small demand on resource to the task with high demand on resource, so as to increase the granularity of the logic core occupied by the task with high demand on resource; when the existing load of the system is changed or the task enters the new running phase, the resource allocator will timely make adjustments in the next operation system dispatching, so as to fully utilize the chip resources.

Description

technical field [0001] The invention relates to operating system design and runtime support in the field of computer system structure, in particular to a resource allocation method for reconfigurable multi-core processors with task number and performance awareness Background technique [0002] Introduction of dynamic reconfigurable multi-core processor technology and resource allocation algorithm based on dynamic reconfigurable multi-core processor [0003] Dynamic Reconfigurable Chip Multiprocessor (DRCMP) is a new type of multi-core processor architecture proposed by academic circles in recent years. The DRCMP chip is composed of a group of isomorphic physical processing units with simple structure, which we call physical cores. DRCMP can dynamically reconstruct a logical logical core composed of one or more physical cores at runtime. Tasks run on logical cores. The more physical cores that constitute a logical core, the greater the granularity of this logical core. Th...

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Application Information

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IPC IPC(8): G06F9/50
Inventor 安虹高晓川王涛邱晓杰韩文廷张爱民
Owner UNIV OF SCI & TECH OF CHINA
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