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Resource allocation method for task number and performance-aware reconfigurable multi-core processors

A multi-core processor and resource allocation technology, applied in resource allocation, multi-programming devices, etc., can solve problems such as reduced efficiency, achieve the effects of reducing average turnaround time, improving system throughput and chip resource utilization

Active Publication Date: 2017-07-28
UNIV OF SCI & TECH OF CHINA
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If the efficiency of the task is greater than the maximum efficiency, it means that the logical core occupied by the task is too small to meet the demand, and the logical core is appropriately increased to reduce the efficiency

Method used

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  • Resource allocation method for task number and performance-aware reconfigurable multi-core processors
  • Resource allocation method for task number and performance-aware reconfigurable multi-core processors

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Embodiment Construction

[0045] The purpose, advantages and key technologies of the present invention will be explained through the following specific implementation methods. This implementation is only a typical example of the solution, and any technical solution formed by replacement or equivalent transformation falls within the scope of protection claimed by the present invention. This section applies the invention to support dynamic resource allocation on a typical DRCMP structure (TFlex).

[0046] In the TFlex structure, there are a total of 32 physical cores on the chip, and the maximum number of tasks that can run simultaneously is 16. There are 1, 2, 4, 8, and 16 logical cores in total, namely logical cores composed of 1, 2, 4, 8, and 16 physical cores. During the task jittering stage or the performance information collection stage of the system, the logic cores are evaluation-type, and their number and granularity depend on the number of concurrently running tasks. If the number of tasks ru...

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Abstract

A resource allocation method for reconfigurable multi-core processors with task number and performance awareness. Dynamic reconfigurable multi-core processors have the ability to dynamically reconfigure on-chip resources during runtime. In order to reduce the average turnaround time of tasks, improve system throughput and chip Resource utilization offers huge room for optimization. In the present invention, within each operating system scheduling interval, the resource allocator first allocates logic cores on average according to the number of tasks, and after running for a certain clock cycle, sorts them according to the performance of the tasks (reflecting the resource requirements of the tasks), and finds Assign tasks with small resource requirements, reduce the granularity of logical cores occupied, and allocate idle physical cores obtained from tasks with small resource requirements to tasks with high resource requirements, so as to increase the number of tasks with high resource requirements The granularity of logical cores occupied. When the current load of the system changes or the task itself enters a new running stage, the resource allocator will make timely adjustments in the next operating system scheduling to make full use of chip resources.

Description

technical field [0001] The invention relates to operating system design and runtime support in the field of computer system structure, in particular to a resource allocation method for reconfigurable multi-core processors with task number and performance awareness Background technique [0002] Introduction of dynamic reconfigurable multi-core processor technology and resource allocation algorithm based on dynamic reconfigurable multi-core processor [0003] Dynamic Reconfigurable Chip Multiprocessor (DRCMP) is a new type of multi-core processor architecture proposed by academic circles in recent years. The DRCMP chip is composed of a group of isomorphic physical processing units with simple structure, which we call physical cores. DRCMP can dynamically reconstruct a logical logical core composed of one or more physical cores at runtime. Tasks run on logical cores. The more physical cores that constitute a logical core, the greater the granularity of this logical core. Th...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/50
Inventor 安虹高晓川王涛邱晓杰韩文廷张爱民
Owner UNIV OF SCI & TECH OF CHINA
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