Semiconductor test fixture and fabricating method thereof

Abstract

Disclosed are a semiconductor test fixture and a fabricating method thereof. The semiconductor test fixture comprises a base and at least one row of test probes arranged on the base. Every two adjacent test probes in each row are in dislocation arrangement. Each test probe comprises a first test pin, an insulation layer and a second test pin. Each test pin comprises a first body, a first test end at one end of the first body and a first connecting end at the other end of the first body. The insulation layer is arranged on the surface of the first body of the first test pin. Each second test pin which is arranged on the surface of the insulation layer and further arranged around the first test pin is co-axial with the first test pin. Each second test pin comprises a second body, a second test end arranged at one end of the second body and a second connecting end at the other end of the second body. The surface of each second test end aligns to that of each first test end. According to the dislocation of the adjacent test probes, distance of adjacent probes is reduced, and electrical property of tested terminals with small distances is tested.

Description

technical field [0001] The invention relates to the technical field of semiconductor testing, in particular to a semiconductor testing fixture and a forming method thereof. Background technique [0002] The test process is to test the electrical function of the packaged product after the IC is packaged to ensure the integrity of the IC function in the factory, and to classify the tested products according to their electrical function as an evaluation of different grades of IC products. According to the basis, and finally the appearance inspection of the product. [0003] The electrical function test is to test various electrical parameters of the product to ensure that the product can work normally. [0004] The traditional two-point contact test on the same terminal under test, such as the Kelvin test, mostly uses double thimbles or double golden fingers in parallel, which mainly has the following shortcomings: [0005] 1. Low manufacturing accuracy: With the continuous s...

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Problems solved by technology

[0005] 1. Low manufacturing accuracy: With the continuous shrinking of the size of semiconductor products, the size of the terminals to be tested and the distance between different terminals to be tested are also shrinking. In order to comply with this trend, the traditional double thimble or double gold The bottleneck of the finger test method is becoming more and more prominent in the problem of fine spacing, and the accuracy requirements are getting higher and higher, and some of them cannot even be realized.

[0006] 2. The structural strength is weak: in order to realize the two-point contact test in the limited space on the terminal under test, the thimble or golden finger is correspondingly thinner and its mechanical structural strength is also weaker and weaker.

[0007] 3. The service life is short: the test contact head of the traditional thimble or golden finger is more susceptible to wear, especially when the precision is higher and the mechanical strength is relatively low, the degree of wear is greater, thereby reducing the use of test fixtures life

[0008] 4. The test accuracy is low: In order to meet the development needs of semiconductors, the resistance value generated by thinner and thinner thimbles or golden fingers continues to increase. Affect the judgment of the test value; on the other hand, the double thimbles or double gold fingers distributed in parallel are also prone to deviations in the test values ​​due to the displacement deviation between the two; The contact method with two back-to-slopes is adopted, and the contact head is easy to rotate out of the terminal under test due to the spring expansion and contraction torque in the overall structure, thereby affecting the test accuracy.

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