FPGA-based high-speed emmc array controller

Abstract

The invention discloses an FPGA-based high-speed eMMC array controller, which comprises a high-speed eMMC array controller IP core, the high-speed eMMC array controller IP core is implemented on the FPGA, and the high-speed eMMC array controller IP core is configured on the FPGA. There is a user management interface and a user data interface, and the high-speed eMMC array controller IP core is respectively connected with a data cache random access memory and several eMMC chipsets, and the eMMC chipset consists of several eMMC chips, and the several Each eMMC chip is mounted on the same eMMC bus, and the beneficial effects of the present invention are as follows: the potential performance of the eMMC chip can be effectively released, the data throughput can be balanced by the built-in / external buffer cache, and the eMMC chip can be operated in a packet flow mode to achieve Maximized contiguous memory bandwidth with easy-to-use front-end data input / output interfaces. It is suitable for high-frequency acquisition records, communication data records, bus data records and other applications that have high requirements on storage capacity, bandwidth, and reliability.

Description

technical field [0001] The present invention relates to the technical field of array controllers, in particular to an FPGA-based high-speed eMMC array controller Background technique [0002] FPGA (Field-Programmable Gate Array), that is, Field Programmable Gate Array. Its characteristics are as follows: 1) ASIC circuits (application-specific integrated circuits) are designed using FPGA, and users can obtain suitable chips without putting them into production. 2) FPGA can be used as a sample piece of other full-custom or semi-custom ASIC circuits. 3) There are abundant flip-flops and I / O pins inside the FPGA. 4) FPGA is one of the devices with the shortest design cycle, the lowest development cost and the lowest risk in ASIC circuits. 5) FPGA adopts high-speed CMOS technology, low power consumption, and can be compatible with CMOS and TTL levels. It can be seen that the FPGA chip is one of the best choices for small batch systems to improve system integration and reliabi...

AI Technical Summary

Problems solved by technology

Disadvantages: low bandwidth (the internal bus bandwidth of the processor is limited and shared with the CPU core), the data interface cannot be customized (usually data / address bus, etc.), and the capacity is low (usually only 1 to 2 eMMC memory chips can be mounted);

Disadvantages: single data interface (usually SATA, USB, etc., not easy to integrate in the device), poor scalability (the number of eMMC memory chips mounted is limited, usually less than 16 pieces), continuous bandwidth is not guaranteed (designed for general occasions, not for Sequential read / write is specially optimized), its price is still far from the price of traditional flash memory cards or flash memory chips

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