A single-event flip-resistant static random memory unit

Abstract

The invention discloses a static random access memory unit with single-particle-upset resistance. The static random access memory unit comprises a signal input end, a signal output end, a clock port, a first control node, a second control node, a first memory node, a second memory node, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube. The static random access memory unit disclosed by the invention has the advantages that the delay time of data writing can be reduced, the power consumption is low, and the occupied area is small.

Description

Technical field [0001] The invention belongs to the technical field of integrated circuits, and relates to a storage unit, in particular to a static random storage unit resistant to single event flipping Background technique [0002] With the continuous development of process technology, the critical dimensions of integrated circuits continue to decrease, and the critical charge of the device node also decreases, and the soft errors caused by the single event effect will become more significant. Compared with combinational logic circuits, memory and latches are more susceptible to single event flips because of the lack of a shielding mechanism. For storage chips used in special fields (aerospace, military, etc.), it is necessary to take anti-radiation reinforcement measures for the storage unit. High-performance memory cells should have the characteristics of large critical charge, fast reading and writing speed, and low power consumption. Jahinuzzaman published (Jahinuzzaman S...

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Problems solved by technology

Jahinuzzaman published (Jahinuzzaman S M, Rennie DJ, Sachdev M.A soft error tolerant 10T SRAM bit-cell with differential readcapability [J]. Nuclear Science, IEEE Transactions on Nuclear Science, 2009, 56(6): 3768-3773.) The Quatro-10T unit has high static power consumption and static noise tolerance, but the write delay is relatively large, and it is difficult for the storage node to recover from the transition from low level to high level

The ROCK unit mentioned in ROCK (Rockett Jr LR.An SEU-hardened CMOS data latch design[J].IEEE Transactions on Nuclear Science, 1988, 35:1682-1687.) has good single-event flip stability, But the power consumption and area are larger

The storage mentioned in Zhang published (Guohe Zhang, Jun Shao, Feng Liang and DongxuanBao, "Anovel single event upset hardened CMOS SRAM cell," IEICE Electronics Express, Vol.9, No, 3, 140-145, 2012.) unit, which has the advantage of short recovery time, but write time and area cost restrict its application

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