Method for forming shallow trench isolation structure

An isolation structure, shallow trench technology, applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems affecting yield, device leakage, changes in device electrical properties, etc., to reduce insulation performance, avoid leakage, The effect of preventing changes in electrical properties

Active Publication Date: 2015-04-15
CSMC TECH FAB2 CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This damage will cause changes in the electrical properties of the device, reduce the insulation performance of STI, cause device leakage, and affect the yield

Method used

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  • Method for forming shallow trench isolation structure
  • Method for forming shallow trench isolation structure
  • Method for forming shallow trench isolation structure

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Embodiment Construction

[0031] In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0032] First of all, "one embodiment" or "embodiment" referred to herein refers to a specific feature, structure or characteristic that may be included in at least one implementation of the present invention. "In one embodiment" appearing in different places in this specification does not all refer to the same embodiment, nor is it a separate or selective embodiment that is mutually exclusive with other embodiments.

[0033] Secondly, the present invention is described in detail using schematic diagrams, etc. When describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and t...

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Abstract

The invention provides a method for forming a shallow trench isolation structure, comprising the following steps: providing a substrate, wherein a pad oxide layer and a silicon nitride layer are sequentially formed on the substrate, and openings exposing the substrate are formed in the pad oxide layer and the silicon nitride layer; forming shallow trenches on the substrate along the openings; forming a protective oxide layer covering the surfaces of the shallow trenches; forming a first oxide layer covering the protective oxide layer and filling the shallow trenches; back-etching the first oxide layer; forming a supplementary oxide layer covering part of the protective oxide layer; forming a second oxide layer covering the protective oxide layer and the supplementary oxide layer; flattening the first oxide layer, the second oxide layer and the protective oxide layer until the silicon nitride layer is exposed; and removing the silicon nitride layer. The method can avoid the change of electrical properties of devices caused by damage of silicon oxide on the top of side walls, improve the insulating performance of STI, and prevent electric leakage of devices.

Description

【Technical field】 [0001] The invention relates to the technical field of semiconductor design and manufacture, in particular to a method for forming a shallow trench isolation structure. 【Background technique】 [0002] With the continuous shrinking of the feature size of semiconductor devices, the isolation area between devices must also be reduced accordingly. For components below 0.18μm, STI (shallow trench isolation, shallow trench isolation) isolation technology is mostly used. The steps mainly include the etching of the STI, the growth of silicon oxide on the sidewall of the active region, and the filling of silicon oxide in the STI. For some high-voltage device products, such as deep STI trenches (>8000 Angstroms), it is difficult to fill the silicon oxide in the STI. If only one-step filling is used, there will be holes in the STI. Therefore, for this type of product , the filling process is refined into three sub-steps, the schematic diagram of which is shown in ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/762
CPCH01L21/76224
Inventor 李健
Owner CSMC TECH FAB2 CO LTD
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