Semi-conductor packaging member and manufacturing method therefor

Abstract

A semi-conductor packaging member and a manufacturing method therefor are disclosed. The manufacturing method comprises the following steps: a first bearing member and a plurality of semi-conductor assemblies are provided, the semi-conductor assemblies have acting surfaces and a plurality of welding pads formed on the acting surfaces, the semi-conductor assemblies are arranged on the first bearing member through the acting surfaces, packaging rubber bodies are formed on the first bearing member to respectively wrap the semi-conductor assemblies, gaps are arranged among the packaging rubber bodies, and a buffer layer is formed on the first bearing member to wrap the packaging rubber bodies and fill the gaps; the first bearing member is removed and therefore the acting surfaces, the welding pads, the packaging rubber bodies and the buffering layer of the semi-conductor assemblies can be exposed. Thus the semi-conductor packaging member and the manufacturing method therefor can prevent the packaging rubber bodies from being warped, and the yield rate of the semi-conductor packaging member can be improved.

Description

technical field [0001] The invention relates to a semiconductor package and a manufacturing method thereof, in particular to a semiconductor package capable of improving yield and a manufacturing method thereof. Background technique [0002] The current fan-out (Fan-Out) type semiconductor package is mainly to package multiple chips by forming an encapsulant on the entire surface of the carrier, but because the contact area between the encapsulant and the carrier is too large, and the encapsulant The coefficient of thermal expansion (Coefficient of Thermal Expansion; CTE) is higher than the thermal expansion coefficient of the carrier, so that the encapsulant is prone to excessive stress and warpage (warpage), thus making it difficult to re-circuit on the encapsulant Cloth and sheet cutting and other processes. [0003] Figure 1A and Figure 1B It is a schematic cross-sectional view illustrating a manufacturing method of a semiconductor package in the prior art. [0004]...

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Problems solved by technology

[0006] The shortcoming of the method for making the above-mentioned semiconductor package is that the contact area between the encapsulant 13 and the release layer 11 on the carrier 10 is too large, and the thermal expansion coefficient and Young's Modulus of the encapsulant 13 are also higher than The thermal expansion coefficient and Young's modulus of the carrier 10 make the encapsulation compound 13 easy to produce such as Figure 1B The situation of the warping shown in the figure thus makes it difficult to carry out subsequent processes such as circuit redistribution and singulation on the encapsulant 13, and reduces the yield of the semiconductor package.

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