semiconductor device

Abstract

The present invention provides a semiconductor device capable of realizing a super junction structure in which electric field concentration is relaxed. The semiconductor device has: a semiconductor region of the first conductivity type formed in the element region and the peripheral region; a plurality of columnar regions of the second conductivity type formed in a ring shape surrounding the element region in the semiconductor region of the peripheral region; A plurality of field confinement regions of 2 conductivity types, which are respectively connected to at least a part of the upper part of the columnar region and arranged on the upper surface of the semiconductor region in the peripheral region; an insulating film covering the field confinement region and arranged on the semiconductor region in the peripheral region and connecting the field plate electrode through the field confinement region formed on the boundary side of the opening portion of the insulating film and a pair of field confinement regions disposed adjacently from the boundary between the element region and the peripheral region toward the outer edge of the peripheral region contact, and reach the field confinement region on the outer edge side of the pair of field confinement regions via the insulating film.

Description

technical field [0001] The present invention relates to a semiconductor device having a super junction structure of a structure for boosting withstand voltage. Background technique [0002] A MOS transistor with a super junction (SJ) structure (hereinafter referred to as "SJMOS") in which a p-type columnar region and an n-type columnar region are adjacently arranged has the characteristics of high withstand voltage and low on-resistance (for example, refer to patent documents 1). In the SJ structure, in order to completely deplete the drift region during reverse biasing, the ratio of the total amount of impurities in the p-type columnar region to the total amount of impurities in the n-type columnar region needs to be about 1. Therefore, p-type columnar regions and n-type columnar regions are arranged in a regularly repeated pattern within the semiconductor chip. [0003] Patent Document 1 Japanese Patent Application Laid-Open No. 2000-277733 [0004] In order to improve ...

AI Technical Summary

Problems solved by technology

However, in the case of the SJ structure, p-type and n-type columnar regions are formed deeply, so that a depletion layer is generated at a deep position in the semiconductor region when reverse bias is applied.

Therefore, at the outer edge of the semiconductor device, the boundary of the depletion layer changes rapidly from a deep position to the surface, and there is a problem that it is difficult to alleviate the concentration of the electric field.

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