Preparation method of storage unit gate of flash memory

Abstract

The invention discloses a preparation method of a storage unit gate of a flash memory. The preparation method comprises the following steps: (1) successively forming a gate dielectric layer, a floating gate structure layer, an inter-gate dielectric layer and a control gate structure layer on a semiconductor composite structure with a shallow trench isolation structure, and forming a patterning photoresistance layer on the surface of the control gate structure layer; (2) according to the patterning photoresistance layer, etching the control gate structure layer to remove parts of the control gate structure layer; (3) carrying out synchronous etching on the control gate structure layer, the inter-gate dielectric layer and the floating gate structure layer to cause parts of the floating gate structure layer to be remained; and (4) etching the remained floating gate structure layer by a high-selection-ratio etching technology to completely remove the floating gate structure layer. Since the preparation method adopts a method of the synchronous etching of the inter-gate dielectric layer and the floating gate structure layer, the etching method can effectively reduce the loss of a shallow trench isolation zone and is simple in technology; the production time is shortened; and the production efficiency is improved.

Description

technical field [0001] The invention relates to a semiconductor manufacturing technology, in particular to a method for preparing a storage unit gate of a flash memory. Background technique [0002] Flash memory is the main non-volatile memory device in the market now, and is widely used in digital equipment such as mobile phones and handheld computers. [0003] Such as figure 1 As shown, the gate of the memory cell region of the flash memory is composed of a control gate structure layer 1 , an inter-gate dielectric layer 2 , a floating gate structure layer 3 , a gate dielectric layer 4 , a silicon substrate 5 , and a shallow trench isolation region structure 6 . The conventional control gate etching method is as follows: the control gate structure layer 1 is etched first, and ends when it contacts the inter-gate dielectric layer 2; then the control gate structure layer 1 between the floating gate structure layers 3 is removed; continue Etching the gate dielectric layer 4 ...

AI Technical Summary

Problems solved by technology

It can be seen that the improved method still uses the conventional photolithography process and dry etching, which will also cause losses to the shallow trench isolation region or the floating gate layer due to the step height between the floating gate structure layer and the shallow trench isolation structure. or the shallow trench isolation region and the floating gate layer cause losses at the same time

Have adverse effects on subsequent processes, and ultimately affect the performance and reliability of semiconductor devices

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