Multi-module time sequence control circuit
A timing control circuit, multi-module technology, applied in the direction of program control, computer control, general control system, etc., can solve the problem of high product cost, and achieve the effect of reducing product cost, high sensitivity and simple circuit structure
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Embodiment 1
[0022] Embodiment 1, this embodiment proposes a multi-module timing control circuit, such as figure 1 As shown, it includes a delay circuit and a shaping circuit, and the delay circuit and the shaping circuit are connected to each module in a one-to-one correspondence, that is, if multiple modules need to be controlled, a set of timing control circuits need to be set for each module separately, The input end of the delay circuit is connected to the signal detection end, and the detection end is used to detect the plug state of the joint and generate a detection signal, and the output end is connected to the input end of the shaping circuit, and the output end of the shaping circuit is connected to the input end of the shaping circuit. Corresponding to the enable terminal connection of the module. The multi-module timing control circuit of this embodiment is built by using a delay circuit combined with a shaping circuit, and only limited electronic components are used. For exam...
Embodiment 2
[0026] Embodiment 2. This embodiment provides a circuit schematic diagram of another embodiment of the switch circuit in the multi-module timing control circuit, as shown in Figure 4 As shown, the first switch circuit is realized by the first NMOS transistor Q1, the second switch circuit is realized by the second NMOS transistor Q2, the gate 1 of the first NMOS transistor Q1 is connected to the detection terminal, and the gate 1 is connected to the drain 3, the source 2 is connected to the first resistor R1, the source of the second NMOS transistor Q2 is connected to the detection terminal through the second resistor R2, the gate 1 and the drain 3 are connected to the ground terminal through the capacitor C1, When the first NMOS transistor Q1 outputs a high level at the detection terminal, the voltage of the gate 1 is greater than the voltage of the source 2, and then the first NMOS transistor Q1 is turned on, and the power-on delay circuit works, and the second NMOS transisto...
Embodiment 3
[0029] Embodiment 3. This embodiment provides a circuit schematic diagram of another embodiment of the shaping circuit in the multi-module timing control circuit. Other circuit parts are the same as those described in Embodiment 1 or Embodiment 2, and will not be repeated here. . like Figure 5 As shown, the shaping circuit of this embodiment includes the first inverter U1 and the second inverter U2 connected in sequence. When the detection terminal does not detect the signal that the device is unplugged, the output is low. Therefore, the second inverter An inverter U1 inputs a low level, and outputs a high level to the second inverter U2 after being inverted by the first inverter U1, and the second inverter U2 inverts the high level again, and outputs a low level Level, the output terminal of the second inverter U2 is connected to the enable terminal of the module it controls, so the enable terminal of the module inputs a low level, and the module does not work when powered ...
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