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Method of making an asymmetric finfet

An asymmetric, semi-conductor technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as S-slope degradation, and achieve the effect of simplifying process steps

Active Publication Date: 2018-03-20
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, compared with 3T-FinFET, 4T (4-Terminal)-FinFET with such a structure will degrade the S-slope (S-slope)

Method used

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  • Method of making an asymmetric finfet
  • Method of making an asymmetric finfet
  • Method of making an asymmetric finfet

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Embodiment Construction

[0023] Next, the present invention will be described more fully with reference to the accompanying drawings, in which embodiments of the invention are shown. However, this invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

[0024] It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer. A layer may be on, adjacent to, connected to, or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when a...

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PUM

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Abstract

The invention discloses a method for fabricating an asymmetric FinFET, comprising: providing an SOI substrate, the SOI substrate comprising a semiconductor substrate, a buried insulating layer on the semiconductor substrate, and a semiconductor material layer on the buried insulating layer; A first opening exposing the buried insulating layer is formed in the semiconductor material layer; a first dielectric layer is formed on the sidewall of the semiconductor material layer exposed in the first opening; a second opening different from the first opening is formed in the semiconductor material layer , the semiconductor material layer between the first opening and the second opening is formed as a fin; a second dielectric layer is formed on the sidewall of the semiconductor material layer exposed in the second opening, wherein the thickness of the second dielectric layer is the same as the thickness of the first A dielectric layer has different thicknesses. The method enables the formation of gate dielectric layers of different thicknesses on both sides of the fins to address the problem of S-slope degradation in some devices. The fin fabrication can be completed while the gate dielectric layers with different thicknesses are formed, which simplifies the process steps.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a method for manufacturing an asymmetric FinFET. Background technique [0002] The continuous reduction in the size of semiconductor devices is a major factor driving the improvement of integrated circuit manufacturing technology. Due to the limitation of adjusting the thickness of the gate oxide layer and the junction depth of the source / drain, it is difficult to shrink the conventional planar MOSFET device to a process below 32nm. Therefore, a multi-gate field-effect transistor (Multi-Gate MOSFET) has been developed ). A Multi-Gate Field Effect Transistor is a type of MOSFET that incorporates multiple gates into a single device, meaning that the channel is surrounded by multiple gates on multiple surfaces, thus better suppressing the "off" state leakage current. In addition, multiple gate field effect transistors can enhance the drive current in the "on" state. [00...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L21/28
Inventor 韩秋华孟晓莹
Owner SEMICON MFG INT (SHANGHAI) CORP