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Shared interrupt multi-core architecture for low power applications

A power consumption, microcontroller technology, applied in the field of multi-core architecture, can solve the problem that the microcontroller does not have the ability to execute tasks assigned by the core

Active Publication Date: 2015-05-27
NXP BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, typical microcontrollers do not have the ability to assign tasks to different cores

Method used

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  • Shared interrupt multi-core architecture for low power applications
  • Shared interrupt multi-core architecture for low power applications
  • Shared interrupt multi-core architecture for low power applications

Examples

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Embodiment Construction

[0020] image 3 A multi-core architecture 300 is shown having cores 310 , 320 . . . and 330 in accordance with an embodiment of the invention. Core 310 contains memory 365 , core 320 contains memory 370 . . . and core 330 contains memory 375 . Cores 310 , 320 . . . 330 are connected to general memory 340 through general memory bus 380 . Cores 310, 320... and 330 are connected to general peripherals 372 and 374, eg, timers, universal asynchronous receiver / transmitter (UART), general purpose input / output, respectively, by general purpose interrupt lines 386 and 385, respectively (GPIO), Serial Peripheral Interface Bus (SPI), Inter-Integrated Circuit Bus (I2C), Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC). image 3 In the exemplary embodiment shown in , non-generic peripherals 370 and 376, such as timers or analog-to-digital converters (ADCs), are connected to cores 310 and 330 via dedicated interrupt lines 387 and 388, respectively. This exemplary e...

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Abstract

A multicore architecture is configured to exploit explicit task parallelism to save power by sharing interrupt sources that trigger independent tasks.

Description

technical field [0001] The present invention relates to a multi-core architecture for shared interrupts for low power applications. Background technique [0002] Employing parallel architectures in processors is a typical way to reduce power consumption with no performance penalty at the architectural level, see, for example, "Low Power Digital CMOS Design", Journal of IEEE Solid-State Circuits, pp. 473-484, 1992 April. For a given level of performance, the use of parallelism allows distribution of tasks, and frequency and voltage can often be scaled down without performance loss. [0003] There is a trend to use multi-core architectures in small microcontrollers. The challenge is often how to efficiently and beneficially use the extra resources available in multi-core architectures. [0004] Applications in the field of small microcontrollers are often based on interrupts that trigger the execution of multiple tasks. figure 1 A system 100 is shown using a number of peri...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/167G06F1/32
CPCG06F1/3243G06F1/3296G06F13/24Y02D10/00
Inventor 胡安·迪亚哥·埃切韦里·埃斯科瓦尔乔斯·德耶稣·皮尼达·德基韦斯
Owner NXP BV