Instruction set transition system and method

Abstract

The invention provides an instruction set transition system and method. According to the arrangement, an external instruction is transited into an internal instruction for execution of a processor core; besides, through configuration, an instruction set supported by a processor system is conveniently expanded. The invention further provides a real-time transition method for an internal instruction address and an external instruction address. Thus the processor core is allowed to directly read the internal instruction in a higher-level cache, and assembly line depth is lowered.

Description

technical field

[0001] The invention relates to the fields of computer, communication and integrated circuit. Background technique

[0002] At present, if programs belonging to different instruction sets need to be executed on a certain processor core, the most common method is to use a software virtual machine (or virtualization layer). The function of the virtual machine is to translate or interpret the program composed of the instruction set (external instruction set) not supported by the processor core, and generate instructions corresponding to the instruction set (internal instruction set) supported by the processor core itself for execution. Generally speaking, the method of interpretation is to use the virtual machine to sequentially take out the various fields in the external instructions, including opcodes and operands, through software methods in real time during the running process, and then use the stack structure implemented in the memory. The code performs th...

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