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Storage unit of static random access memory based on dice structure

A static random access memory cell technology, applied in the fields of static random access memory, integrated circuit design and manufacturing, can solve the problems of excessive area and large number of transistors, and achieve the effect of small area overhead and reduced number

Active Publication Date: 2017-08-25
INST OF AUTOMATION CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The disadvantage of this method is that there are too many transistors and the area is too large

Method used

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  • Storage unit of static random access memory based on dice structure
  • Storage unit of static random access memory based on dice structure
  • Storage unit of static random access memory based on dice structure

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0020] like Figure 7 As shown, this embodiment includes a redundant information latch circuit and a redundant bit selection circuit. The redundant information latch circuit is composed of NMOS transistors N0, N1, N2, and N3 connected end to end; the gate of N0 is connected to the drain of N1 and connected to the storage point X1; the gate of N1 is connected to the drain of N2 and connected to to the storage point X2; the gate of N2 is connected to the drain of N3 and connected to the storage point X3; the gate of N3 is connected to the drain of N0 and connected to the storage point X0; the sources of N0, N1, N2 and N3 are all grounded. The redundant bit selection circuit is composed of PMOS transistors P0, P1, P2, and P3; the drain of P0 is connected to X0, the drain of P1 is connected to X1, the drain of P2 is connected to X2, and the drain of P3 is connected to X3; the source of P0 and P2 The poles are connected together to the bit line BL; the sources of P1 and P3 are co...

Embodiment 2

[0027] like Figure 8 As shown, it also includes a redundant information latch circuit and a redundant bit selection circuit. The redundant information latch circuit is composed of PMOS transistors P0, P1, P2, and P3 connected end to end; the gate of P0 is connected to the drain of P3 and connected to the storage point X3; the gate of P1 is connected to the drain of P0 and connected to To storage point X0; the gate of P2 is connected to the drain of P1 and connected to storage point X1; the gate of P3 is connected to the drain of P2 and connected to storage point X2; the sources of P0, P1, P2, and P3 are connected Together, connect to the power supply. The redundant bit selection circuit is composed of NMOS transistors N0, N1, N2, and N3. The drain of N0 is connected to X0, the drain of N1 is connected to X1, the drain of N2 is connected to X2, and the drain of N3 is connected to X3; the sources of N0 and N2 are connected together and connected to the bit line BL; the source...

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Abstract

The present invention proposes a storage unit of a static random access memory based on a DICE structure, including a redundant information latch circuit and a redundant bit selection circuit, and the redundant information latch circuit is composed of 4 MOS transistors, including 4 data storage points ; The redundant bit selection circuit is also composed of 4 MOS tubes, and the drains of MOS tubes M0, M1, M2, and M3 are respectively connected to 4 data storage points X0, X1, X2, and X3; the sources of M0, M2 are connected to Together, they are connected to the bit line BL; the sources of M1 and M3 are connected together and connected to the bit line BLB; the gates of the four MOS transistors are connected together and connected to the word line WL. The present invention does not increase obvious complexity and only increases a small amount of area to ensure that the storage unit does not undergo state reversal when it is bombarded by particles and ensures correct data.

Description

technical field [0001] The invention belongs to integrated circuit design and manufacturing technology, relates to static random access memory, in particular to a storage unit of static random access memory based on DICE structure, which can be applied to military field, civilian field and commercial space field, especially for high Performance High Density Radiation Hardened Applications. Background technique [0002] Single event flipping is an important parameter for radiation hardening. A single event upset, or soft error, is a non-destructive data transition on a data storage bit. Charged particles (such as cosmic rays or trapped protons) are injected into semiconductor devices and quickly lose energy by interacting with semiconductor materials. The lost energy causes electrons to jump from the valence band to the conduction band. Thus, there are electrons in the conduction band, leaving holes in the valence band, forming electron-hole pairs, and introducing non-equi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/413
Inventor 刘丽王静秋陈亮
Owner INST OF AUTOMATION CHINESE ACAD OF SCI
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