A Port ESD Structure and Its Equivalent Circuit Based on HVNMOS Withstands Positive and Negative High Voltage

Abstract

The invention discloses a port ESD structure and its equivalent circuit based on HVNMOS resistant to positive and negative high voltages. The port ESD structure includes a first NBL buried layer, a second NBL buried layer, a first N+ active region connected to a power supply, and a second NBL buried layer. The second N+ active region, the third N+ active region, the fourth N+ active region and the first N well, the second N well, the third N well, and the fourth N well; the first P+ active region, the second The first P well with the P+ active region in contact; the second P well with the third P+ active region and the fourth P+ active region as contacts; and the fifth P+ active region connected to GND. The equivalent circuit includes a first MOS transistor N1 and a second MOS transistor N2; the gate of the first MOS transistor N1 is connected to the gate of the second MOS transistor N2, and the source of the first MOS transistor N1 is connected to the second MOS transistor N2 The source is connected, the source of the first MOS transistor N1 is also connected to the gate of the first MOS transistor N1, the drain of the first MOS transistor N1 is connected to the port PAD, and the drain of the second MOS transistor N2 is grounded. While the invention has positive and negative high voltage resistance characteristics, it can also meet the requirements of ESD protection.

Description

technical field [0001] The invention belongs to the field of semiconductor technology, and more specifically relates to a port ESD structure based on HVNMOS capable of withstanding positive and negative high voltages and an equivalent circuit thereof. Background technique [0002] With the shrinking of the size of the semiconductor process, the gap between the working voltage of the device and the breakdown voltage is getting smaller and smaller, and the electrostatic discharge (ESD) problem of the integrated circuit is becoming more and more significant. Usually, the working voltage of the IC port is between 0V and the power supply voltage, so the ESD structure of the port only needs to ensure that the ESD device has no leakage current when the port voltage is between 0V and the power supply voltage. In some interface chips, there will be a negative voltage where the port voltage is higher than the power supply voltage or lower than zero potential. At this time, the ESD str...

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Problems solved by technology

[0003] In view of the above defects or improvement needs of the prior art, the present invention provides a positive and negative high voltage port ESD device based on HVNMOS, the purpose of which is to make the signal port ESD structure have the characteristics of positive and negative high voltage resistance and also meet the ESD protection design Requirements, thereby solving the technical problem that there is no positive and negative high voltage port ESD protection in the prior art

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