Clock phase correcting circuit

Abstract

The invention belongs to the technical field of clock correcting, and provides a clock phase correcting circuit. According to the circuit, a digital expression signal of a target phase is compiled through a decoding circuit to obtain a corresponding digital control signal, a current synthesis circuit is controlled by the digital control signal to output a corresponding bias voltage, and a phase synthesis circuit receives a reference clock and synthesizes a required clock phase under the control of the bias voltage. The clock correcting is achieved through the digital control signal, and therefore the sample clock can be conveniently adjusted and corrected at any angle, various data clock recovery schemes are established, and the design complexity of a system is lowered. Compared with the prior art, the clock phase correcting circuit has the advantages that a phase-locked loop simulating device is omitted, the clock extraction or compensation accuracy is improved, and therefore the transmission quality and transmission speed of communication signals can be increased, and the circuit is particularly suitable for extracting or correcting clock signals in the high-speed serial communication system.

Description

technical field [0001] The invention belongs to the technical field of clock correction, in particular to a clock phase correction circuit. Background technique [0002] At present, in the data communication system, with the gradual increase of the data transmission rate, the synchronous transmission of the sampling clock becomes more and more difficult, which requires the clock signal to be embedded into the data signal through a special coding method. Therefore, in the interface circuits (such as: PCIE interface circuit, USB interface circuit) of the current high-speed serial communication system, a set of differential lines are used to transmit the clock signal and the data signal at the same time. [0003] In order to extract the clock signal from the data signal, the prior art provides a clock and data recovery system, which uses a phase-locked loop to directly extract and recover the clock signal from the data signal. Specifically, the system includes a phase-locked l...

AI Technical Summary

Problems solved by technology

[0005] The purpose of the embodiment of the present invention is to provide a clock phase correction circuit, which aims to solve the problem that the clock and data recovery system used in the existing high-speed serial communication system uses a phase-locked loop to directly extract and recover the clock signal from the data signal. Due to the reason of the phase-locked loop itself, there is a problem of deviation in the recovered clock signal

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