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Production method for traps of integrated circuit

A manufacturing method and integrated circuit technology, applied in the direction of circuits, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problems of high cost of photolithography process and high process cost, and achieve the effect of saving photolithography times and low cost

Active Publication Date: 2015-07-01
FOUNDER MICROELECTRONICS INT
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

As we all know, the cost of photolithography process is very high, which leads to the high process cost of the above traditional methods

Method used

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  • Production method for traps of integrated circuit
  • Production method for traps of integrated circuit
  • Production method for traps of integrated circuit

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Embodiment Construction

[0033] The present invention is described more fully below with reference to the accompanying drawings that illustrate embodiments of the invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

[0034] The number of the first N well, the second N well, the first P well, and the second P well in the integrated circuit is not limited, and the positional relationship of each well is not particularly limited. For the convenience of expression, the manufacturing method of the integrated circuit well provided by the present invention will be described in detail below by taking a first N well, a second N well, a first P well and a second P well as examples respectively.

[0035] The manufacturing method of the well of integrated circuit provided by the present invention, its technological process is as follows:

[0036] , grow an initial oxide layer 2 (thickness T0) on the surface of the...

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Abstract

The invention provides a production method for traps of an integrated circuit. The production method comprises the following steps of growing an initial oxide layer, depositing silicon nitride and coating photoresist on the surface of a substrate in sequence; carrying out photo-etching for the first time and forming a first element doping zone and a first oxide layer in a first default zone; coating the photoresist again and removing the photoresist in a second default zone, wherein the second default zone comprises a third default zone which is coincident to the first default zone and a fourth default zone which is completely not coincident to the first default zone; forming a second element doping zone and a second oxide layer in the fourth default zone, and forming a third oxide layer in the third default zone; forming a second element doping zone in a zone outside the first default zone and the second default zone; and lastly, carrying out heat treatment on the substrate so as to diffuse a first element and a second element to form a P trap and an N trap. In comparison with the conventional method, the photo-etching frequency is saved and the cost is reduced.

Description

technical field [0001] The invention relates to a method for manufacturing a well of an integrated circuit, and belongs to the technical field of semiconductor device manufacturing. Background technique [0002] Semiconductors that are pure and have a complete crystal structure are called intrinsic semiconductors, such as intrinsic silicon and intrinsic germanium. The semiconductor material commonly used in integrated circuits is silicon. Artificially doping impurity elements in intrinsic semiconductors forms impurity semiconductors, for example: doping VA group elements in intrinsic silicon, the formed impurity semiconductors are N-type semiconductors; doping IIIA group elements in intrinsic silicon, The formed impurity semiconductor is a P-type semiconductor. According to the amount of doped impurities, that is, the doping concentration of N-type semiconductors or P-type semiconductors, impurity semiconductors can be divided into two types: heavily doped and lightly doped...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/3105H01L21/265
CPCH01L21/02233H01L21/266
Inventor 潘光燃文燕石金成高振杰王焜
Owner FOUNDER MICROELECTRONICS INT
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