Semiconductor device and forming method thereof and method for improving cutting yield of wafer

Abstract

Disclosed are a semiconductor device and a forming method thereof and a method for improving the cutting yield of a wafer. The forming method comprises providing the wafer, wherein the wafer is divided into a plurality of chip areas and cutting channels and every cutting channel is located between the two corresponding adjacent chip areas; forming an interlayer dielectric layer on the wafer; forming a plurality of layers of interconnection metal layers and plugging layers corresponding to the chip areas in the interlayer dielectric layer, wherein every two adjacent interconnection metal layers are electrically connected with each other through the corresponding plugging layer; forming a plurality of layers of pseudo plugging layers corresponding to the cutting channels in the interlayer dielectric layer, wherein every pseudo plugging layer comprises a plurality of pseudo plugs. When the semiconductor device is cut along the cutting channels, the stress produced at the position of every cutting channel is mainly applied to the corresponding pseudo plugs, the stress cannot be produced on or only small stress can be produced on the interlayer dielectric layer portion of the corresponding chip areas and the plugging layers in the interlayer dielectric layer portion, and accordingly fractures of the interlayer dielectric layer portion of the corresponding chip areas and the plugging layers in the interlayer dielectric layer portion are prevented, the good interconnection performance of the interconnection metal layers and the plugging layers of the chip areas is ensured, and accordingly the cutting yield of the wafer is significantly improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a method for forming the same, and a method for improving the wafer cutting yield. Background technique [0002] In the semiconductor manufacturing process, the wafer formed with integrated circuits is usually cut into individual chips, and then these chips are made into semiconductor packaging structures with different functions. [0003] refer to figure 1 , figure 1 It is a top view of the wafer, the wafer is composed of a plurality of chips 10 , and two adjacent chips 10 are separated by scribe lines 11 . For each chip 10, a device structure, an interconnection structure, and pads are formed on a substrate through processes such as deposition, lithography, etching, doping, and heat treatment. Afterwards, the wafer is diced into a plurality of independent chips 10 along the dicing lines 11 , so there are no functional elements at the positions ...

AI Technical Summary

Problems solved by technology

This will cause the loss of the protective effect of the sealing ring, the chip is easily damaged in the packaging structure, and the performance and service life of the chip will be reduced

In addition, if the crack extends into the chip, it will destroy the interconnection structure, the plug layer in the interconnection structure will break, and the signal transmission channel in the interconnection structure will be disconnected, causing the chip to fail, for example, some functions of the chip cannot work normally. Or the performance of the chip does not meet the design requirements

That is, the existing wafer cutting yield is low

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