Semiconductor device test structure and method of forming the same

Abstract

The invention provides a test structure of a semiconductor device and a forming method thereof. The test structure includes: a first semiconductor device structure, including: multiple metal layers separated from each other in a dielectric layer, with a first plug between two adjacent metal layers; and a test unit located in the In the dielectric layer on one side of the first semiconductor device structure, the test unit is separated from the first semiconductor device structure by a predetermined distance, for obtaining a dielectric between multilayer metal layers corresponding to the first semiconductor device structure layer electrical properties. The test structure of the semiconductor device provided by the invention can detect the fracture or delamination phenomenon of the low-K dielectric layer or the ultra-low-K dielectric layer caused by stress accumulation.

Description

technical field [0001] The invention relates to the technical field of semiconductor testing, in particular to a testing structure of a semiconductor device and a forming method thereof. Background technique [0002] At present, low-K materials or ultra-low-K materials are often used as interlayer dielectrics in integrated circuit chips to reduce the distributed capacitance between interconnect lines, reduce signal crosstalk, shorten signal propagation delay, and improve the overall performance of the chip. However, low-K materials and ultra-low-K materials have poor thermal and mechanical properties, weak adhesion to metal layers, and weak mechanical strength. When cutting the wafer, there will be serious delamination or peeling between the metal layer and the interlayer dielectric layer at the edge of the chip; during the wire bonding process, there will be broken soldering, weak soldering or peeling off of the metal layer and the interlayer dielectric layer, resulting in ...

AI Technical Summary

Problems solved by technology

However, low-K materials and ultra-low-K materials have poor thermal and mechanical properties, weak adhesion to metal layers, and weak mechanical strength

When cutting the wafer, there will be serious delamination or peeling between the metal layer and the interlayer dielectric layer at the edge of the chip; during the wire bonding process, there will be broken soldering, weak soldering or peeling off of the metal layer and the interlayer dielectric layer, resulting in IC electrical failure

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