Inter-chip high-speed interconnection link layer design method and system

Abstract

The invention discloses an inter-chip high-speed interconnection link layer design method and system. The method is applied to an inter-chip high-speed interconnection link layer system. The system comprises a plurality of chips. The chips comprise link layer logic circuits and PCS layer logic circuits. The link layer logic circuits comprise data verification modules, protocol package channel management modules and link layer transmission modules. The PCS layer logic circuits comprise link training modules, PCS layer transmission modules, interface control modules, data coding modules, data decoding modules, data scrambling modules and data descrambling modules. The link layer logic circuits are connected with the PCS layer logic circuits. According to the design method and system, fast and efficient transmission of data among the multiple chips can be achieved.

Description

technical field

[0001] The invention relates to the field of integrated circuit design, in particular to a link layer design method and system for realizing inter-chip high-speed interconnection. Background technique

[0002] With the rapid development of semiconductor process technology, the performance of microprocessor (MCU), digital signal processor (DSP), programmable gate array (FPGA) has been greatly improved, making ultra-large-scale complex calculations in practice be more widely applied. But a single processor still cannot meet the growing application requirements. If multiple processors are interconnected into a processor array for multi-core cooperative parallel computing, the data processing capability of the system can be doubled, so the research on multi-core interconnection technology has become a new hot issue.

[0003] Based on the link layer data transmission technology, although the technology has high complexity, it can realize the effective sharing of...

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