Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The demonstration method comprises the steps of forming a plurality of fin lines extending along a first direction on an SOI substrate, wherein the SOI substrate comprises a supporting substrate, an embedded insulating layer and an SOI layer, and the SOI layer with a certain thickness is reserved to extend among the fin lines on the embedded insulating layer after the fin lines are formed; forming a plurality of gate lines extending along a second direction which is intersected with the first direction on the substrate, wherein each gate line is intersected with the corresponding fin line through a gate dielectric layer; forming a dielectric side wall at the side walls of the gate lines; epitaxially growing a semiconductor layer on the SOI layer and the surfaces, which are not covered by the gate lines and the side wall, of the fin lines; forming an insulating isolation portion between devices in a predetermined area, wherein at least one gate line is divided into two or more parts by the corresponding insulating isolation portion, and at least one fin line is divided into two or more parts by the corresponding insulating isolation portion.

Description

technical field [0001] The present application relates to the field of semiconductors, and more particularly, to a semiconductor device including fins and a manufacturing method thereof. Background technique [0002] With the increasing integration density of semiconductor devices, FinFET (Fin Field Effect Transistor) has attracted much attention due to its good electrical performance, scalability and compatibility with conventional manufacturing processes. figure 1 A perspective view of an example FinFET is shown in . Such as figure 1 As shown, the FinFET includes: a substrate 101 ; a fin 102 formed on the substrate 101 ; a gate electrode 103 intersecting with the fin 102 , and a gate dielectric layer 104 is provided between the gate electrode 103 and the fin 102 ; and an isolation layer 105 . In this FinFET, under the control of the gate electrode 103, a conductive channel can be generated in the fin 102, specifically in the three side walls of the fin 102 (the left and ...

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Problems solved by technology

In addition, such a small fin is very prone to collapse during the manufacturing process, especially when forming smaller and smaller fins on SOI (semiconductor-on-insulator) wafers

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