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6 results about "Fin lines" patented technology

Integrated circuit structure and method for fabricating the same

A method for fabricating an integrated circuit structure is provided. The method includes forming an epitaxial stack over a semiconductor substrate, wherein the epitaxial stack comprises a plurality of first epitaxial layers and a plurality of second epitaxial layers alternately arranged over the semiconductor substrate; patterning the epitaxial stack into a first fin and a second fin, wherein from a top view the first fin extends along a first direction, and the second fin has a first fin line extending along the first direction and a second fin line extending along a second direction different from the first direction; forming a first gate structure over a first portion of the first fin; etching a recess in a second portion of the first fin adjacent the first portion of the first fin; and forming a source / drain feature in the recess.
Owner:TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

A terahertz mixer

PendingCN122119526AImplement nonlinear mixingImproved Impedance Matching CharacteristicsMulti-frequency-changing modulation transferenceLocal oscillator signalIntermediate frequency
The application discloses a terahertz mixer, comprising: a radio frequency input waveguide, a local oscillator input waveguide, a local oscillator filter and an intermediate frequency output waveguide, wherein the intermediate frequency output waveguide comprises a built-in fin line transition structure and a Schottky diode pair; one end of the fin line transition structure is connected with the radio frequency input waveguide, the other end of the fin line transition structure is connected with the local oscillator filter, the Schottky diode pair is connected with one side of the fin line transition structure and connected with an intermediate frequency output port of the intermediate frequency output waveguide; after the local oscillator signal is filtered by the local oscillator filter, the local oscillator signal is transmitted to the fin line transition structure, the radio frequency signal and the local oscillator signal are loaded into the Schottky diode pair through the fin line transition structure for frequency mixing, and the intermediate frequency signal is output through the intermediate frequency output port. In this case, the fin line transition structure simultaneously carries the radio frequency signal and the local oscillator signal, which can realize spatial superposition and power efficient injection of the signals, and has good impedance matching characteristics.
Owner:UNIV OF ELECTRONICS SCI & TECH OF CHINA +1

Method for preparing strain channel finfet

PCT designated stageWO2026061119A1Integrated circuit manufacturingLattice mismatch
A method for preparing a strain channel FinFET, which method belongs to the technical field of integrated circuit manufacturing. After the manufacturing of a fin line is completed, amorphous silicon is generated by means of an amorphization implantation method; after being covered by a strain dielectric layer and annealed at a high temperature, the amorphous silicon is recrystallized, and in this case, tensile stress / compressive stress required by an N / PMOS can be formed between the crystalline silicon and a strain dielectric; and a strain dielectric material is then selectively removed to implement the preparation of a strain channel FinFET. In the method, the lattice mismatch between the strain dielectric material and the crystalline silicon is used to generate tensile stress or compressive stress required by a FinFET device. A single strain material is used to realize N / PMOS channel strain, so that the flow of channel stress engineering is simplified, the process complexity is reduced, and the method has the potential to be applied to technology nodes of 14 nm and above.
Owner:PEKING UNIV +1

Millimeter wave SIW filter with adjustable transmission zero and implementation method thereof

The application discloses a millimeter wave SIW filter with adjustable transmission zero point and an implementation method thereof. The filter comprises a substrate composed of an upper metal plating layer, a dielectric integrated substrate and a lower metal plating layer. An input five-fold fin line structure, a resonant cavity and an output five-fold fin line structure are sequentially arranged on the substrate. The resonant cavity is composed of a circular metalized through hole formed on the substrate. A plurality of resonant metalized through holes are further included in the resonant cavity, and the resonant metalized through holes are used for tuning the resonant cavity. The embodiment of the application provides a filter with simple structure, easy processing and flexible and controllable transmission zero point, and can be widely applied to the technical field of filters.
Owner:SUN YAT SEN UNIV

Fin-based well straps for improving memory macro performance

PendingUS20260143661A1DopantDevice material
A method of forming a semiconductor device includes patterning a semiconductor substrate to form a fin line extending continuously from a circuit region of the semiconductor device to a well strap region of the semiconductor device, performing a cutting process to divide the fin line into a first fin-shaped structure in the circuit region and a second fin-shaped structure in the well strap region, epitaxially growing a first epitaxial feature over the first fin-shaped structure in the circuit region and a second epitaxial feature over the second fin-shaped structure in the well strap region, doping the first epitaxial feature with a first dopant of a first conductivity type, and doping the second epitaxial feature with a second dopant of a second conductivity type that is opposite to the first conductivity type.
Owner:TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

Integrated circuit structure and method for fabricating the same

A method for fabricating an integrated circuit structure is provided. The method includes forming an epitaxial stack over a semiconductor substrate, wherein the epitaxial stack comprises a plurality of first epitaxial layers and a plurality of second epitaxial layers alternately arranged over the semiconductor substrate; patterning the epitaxial stack into a first fin and a second fin, wherein from a top view the first fin extends along a first direction, and the second fin has a first fin line extending along the first direction and a second fin line extending along a second direction different from the first direction; forming a first gate structure over a first portion of the first fin; etching a recess in a second portion of the first fin adjacent the first portion of the first fin; and forming a source / drain feature in the recess.
Owner:TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD