Fin manufacturing method

Abstract

The invention discloses a fin manufacturing method which comprises the following steps: forming multiple hard mask lines on a substrate; performing wet etching on the substrate, and forming multiple grooves and multiple initial fins among the grooves; adjusting the sectional morphology of the initial fins, reducing the top and / or bottom widths of the initial fins, and forming the final fins. According to the fin manufacturing method disclosed by the invention, refined fin lines are formed according to a special stepped etching process, and the performance and reliability of the device are improved.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor device, in particular to a method for manufacturing fins of a FinFET device. Background technique [0002] Three-dimensional multi-gate devices such as fin field-effect transistors (FinFETs) and tri-gate (tri-gate) devices are among the most promising new device technologies as device dimensions scale down to 22nm technology and below. The control ability of the gate suppresses leakage and short channel effects. [0003] For the traditional process, the gate patterning and contact formation of CMOS devices including FinFET and tri-gate devices are performed through the following steps in order to realize isolated functional devices: [0004] 1. Using line-and-cut (line-and-cut) dual lithography patterning technology and subsequent etching of the gate stack to pattern the gate; [0005] 2. Use uniform feature size and pitch to print parallel lines for gate patterning in one direction;...

AI Technical Summary

Problems solved by technology

At this point, even with well-uniform epitaxial growth, the fin size for the source / drain regions of the device is still very small, which makes it difficult to form effective contacts on these regions

On the other hand, these very small size fins are also fragile and very prone to breakage or collapse, especially for fins formed on SOI wafers

Therefore, it is very difficult to control the fin height and the shallow trench isolation (STI) used to form FinFETs on bulk silicon wafers

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