Manufacturing method for fin on insulator

Abstract

The invention discloses a manufacturing method for a fin on an insulator. The manufacturing method comprises the following steps: forming the fin on a substrate; forming a side wall on the side wall of the fin; carrying out anisotropic etching on the substrate and forming a bottom structure under the fin; carrying out isotropic etching on the substrate so as to reduce the width of the bottom structure; and carrying out an oxidization or nitriding process on the bottom structure so as to convert the bottom structure into the insulator. According to the manufacturing method for the fin on the insulator disclosed by the invention, a refined fin line is formed by a special sub-step etching process, and good insulated isolation between the substrate and the fin is formed by oxidizing or nitriding the lower part of the fin, so that the device performance and reliability are improved.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor device, in particular to a method for manufacturing FinFET device fins in a semiconductor-on-insulator. Background technique [0002] Three-dimensional multi-gate devices such as fin field-effect transistors (FinFETs) and tri-gate (tri-gate) devices are among the most promising new device technologies as device dimensions scale down to 22nm technology and below. The gate control ability suppresses leakage and short channel effects. [0003] For the traditional process, the gate patterning and contact formation of CMOS devices including FinFET and tri-gate devices are performed through the following steps in order to realize isolated functional devices: [0004] 1. Using line-and-cut (line-and-cut) dual lithography patterning technology and subsequent etching of the gate stack to pattern the gate; [0005] 2. Use uniform feature size and pitch to print parallel lines for gate patterni...

AI Technical Summary

Problems solved by technology

At this point, even with well-uniform epitaxial growth, the fin size for the source / drain regions of the device is still very small, which makes it difficult to form effective contacts on these regions

On the other hand, these very small size fins are also fragile and very prone to cracking, especially for fins formed on SOI wafers

Therefore, it is very difficult to control the fin height and the shallow trench isolation (STI) used to form FinFETs on bulk silicon wafers

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